We have the OMAPL138 with a 25Mhz input clk – PLL SYSCLK2 will multiple to 150Mhz. We set up our UART BCLK divider to 25 and the UART sample rate divider to 13. This will give us an actual baud rate of 461,538 baud. The desired is 460,800. Gives us a error rate of 0.16%. We are noticing when communicating with other equipment that is configured @ 460,800 buad rate a bunch of framing, overflow errors. If we change the other equipment baud rate to 461,538 we get no errors. I would have though @ 0.16% error rate would be more than sufficient for a robust comm link. Does TI have any test data for error rate tolerance on the internal UART in the OMAPL138?
Thanks,
Ben
