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EMIFA asynchronous interface clock issue

Abhishek Konana
Prodigy 100 points

Hello,

                  I was looking into C6457 EMIFA datasheet(sprugk2b)  to configure EMIFA as asynchronous interface, the interface signals in table 6 and interface figures fig 4 to fig 7 there is no CLK signals but when in timing diagram fig 8 and next diagrams he has mentioned about CLK signals so i am trying to  tap signal on FPGA side should I send CLK signal  .

Regards,

Abhishek Konana

  • 0
    TI__Guru* 84110 points

    Abhishek,

    The timing parameters programmed for the EMIFA operation are defined in terms of ECLKOUT cycles, so it is required to show their timing with the ECLKOUT signal in the timing diagram.

    It is not required to connect the ECLKOUT signal to the FPGA if the FPGA can implement a purely asynchronous interface. It may be easier to implement the interface with the ECLKOUT signal, but it is not a requirement.

    Regards,
    RandyP