SPI transmit/receive + GPIO event

Flamingo said:

Using the OMAP-L137, I'm trying to configure DMA SPI transfers. The receiving peripheral will signal when data is ready to read via a GPIO input to the OMAP.

This sounds very similar to the function of the /SPIx_ENA pin.  Have you looked closely at that pin?  It might be cleaner.  I was a little confused on who was master and who was slave in this scenario so I'm not sure if it will work or not, but wanted to make sure you looked at it.

Flamingo said:

Because my receive events will be triggered by my transmits, I'd like to setup the DMA for receive via REVT from the SPI. I'd like to setup the transmit DMA via the received GPIO event. The GPIO pin is in bank 5. The associated event is event 29. Do I need to use PaRAM set 29 to use event 29?

Yes, it's a 1-to-1 mapping (for this device).

Flamingo said:

(Prior to this change, I've set the thing up to use PaRAM sets 8 (Receive) and 9 (Transmit). The data were heinous (because the peripheral can't keep up), but the events occurred as expected.)

Which peripheral?  The other device?  This sounds similar to what the /SPIx_ENA pin was meant to do, if I understand you correctly.

It is identical to the SPI1_ENA, except that the signal was not wired to the SPI1_ENA line. I've had it moved to the correct OMAP-L137 pin, but the offending SPI peripheral defaults this signal to high. I believe this prevents any transmissions to the peripheral.

In order to change that, I need to disable SPI1_ENA while I initialize the peripheral. Then I need to enable it again. I have to get about 4 words transmitted manually before I can let the SPI automatically handle the transfers.

Do I have to disable (SPIGCR1.ENABLE=0) to change the SPIFMT0 register?

I was wrong. It isn't quite the same as SPI_ENA. The timing is very different. That is, my signal stays low only until the SCLKs start, and then is driven high (by the SPI-ADC) again. So I'm back to having to drive it via the Bank 5 event.

Keep in mind that you will only be able to enable ONE pin in Bank 5 in order for this to work properly.  Specifically, only the bit corresponding to your GPIO signal should be set in SET_RIS_TRIG/SET_FAL_TRIG.  If you set more than 1 event in SET_RIS_TRIG/SET_FAL_TRIG then you will initiate the EDMA transfer even when the other GPIOs toggle!

I have only one thing in bank 5 that I've enabled. I've posted a related issue: I don't seem to be able to enable event 29 in the Edma event register! I'll be experimenting further.