I'm trying to figure out why my SPI/EDMA implementation times out. Associated with that, I'm trying to figure out how to interpret the debug registers for the EDMA device. Here is some debug output for a case that failed.
Original program for PaRAM sets:
[DSP] @6,812,612tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[0] = 0x81c08001
[DSP] @6,812,652tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[1] = 0x1e12040
[DSP] @6,812,691tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[2] = 0x10002
[DSP] @6,812,729tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[3] = 0xc24ae500
[DSP] @6,812,768tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[4] = 0x20000
[DSP] @6,812,806tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[5] = 0x10460
[DSP] @6,812,843tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[6] = 0x20000
[DSP] @6,812,881tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 8[7] = 0xff00
[DSP] @6,812,918tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[0] = 0x81908001
[DSP] @6,812,957tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[1] = 0x1e12040
[DSP] @6,812,996tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[2] = 0x10002
[DSP] @6,813,034tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[3] = 0xc24ce300
[DSP] @6,813,074tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[4] = 0x20000
[DSP] @6,813,111tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[5] = 0x1ffff
[DSP] @6,813,149tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[6] = 0x20000
[DSP] @6,813,194tk: [+1 T:0xc272f98c] DSP_TSK - InitializeCollectionDMA> PaRAM set 35[7] = 0x1270
After the timeout:
[DSP] @7,986,260tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> Timed out waiting for DMA to complete.
[DSP] @7,986,298tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> TCCFG = 0x212
[DSP] @7,986,330tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> TCSTAT = 0x1100
[DSP] @7,986,362tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> ERRSTAT = 0x0
[DSP] @7,986,391tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> ERRDET = 0x0
[DSP] @7,986,422tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SAOPT = 0x108030
[DSP] @7,986,454tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SASRC = 0xc2473efe
[DSP] @7,986,488tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SACNT = 0x2
[DSP] @7,986,517tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SABIDX = 0x20002
[DSP] @7,986,549tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SAMPPRXY = 0x101
[DSP] @7,986,581tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SACNTRLD = 0x2
[DSP] @7,986,611tk: [+7 T:0xc272f98c] DSP_TSK - Fxn_collect> SASRCBREF = 0xc2473efe
[DSP] @7,986,646tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[0] = 0x81c08001
[DSP] @7,986,682tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[1] = 0x1e12040
[DSP] @7,986,718tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[2] = 0x10002
[DSP] @7,986,751tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[3] = 0xc24ae500
[DSP] @7,986,787tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[4] = 0x20000
[DSP] @7,986,822tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[5] = 0x10460
[DSP] @7,986,856tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[6] = 0x20000
[DSP] @7,986,890tk: [+1 T:0xc272f98c] DSP_TSK - Fxn_collect> PaRAM set 8[7] = 0xff00
I believe that the debug registers are for PaRAM set 8 because the TCC field of SAOPT is 8. However, this is a linked transfer, so it could be for PaRAM set 35, I guess.
As you can see, I've printed out the values programmed into PaRAM set 8 just below the debug registers.
1. Documentation says that the top 16 bits of SABIDX always reads as zero. I'm seeing a 0x2. Why?
2. The documentation says that SASRC is the "Source address for program register set. EDMA3TC updates the value according to source addressing mode (SAM bit in the source active options register, SAOPT)." I don't know what the "program register set" is. If it were the source pointer programmed into PaRAM set 8, then it should be 0x1e12040.
3. I had programmed non-incrementing addressing for the source (which is the SPI1 receive buffer). Why does SAOPT show that both src and dst are incrementing?
Any help interpreting these is appreciated.