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Question regarding EVM: VREFCA and VREFDQ input of 0.75V

Other Parts Discussed in Thread: TPS51116

Hello,

I have the following question from a customer working with the TMDXEVM8148.

Why does the EVM use a voltage divider to generate the 0.75V for the VREFCA and VREFDQ inputs of the DDR3 and the VREFSSTL_DDR input of the 8168? Instead of using the VTT_REF output of the TPS51116?

Thank you for your help,

Chuchen Wang

  • Hi Chuchen,

    The DM8148 EVM DDR3 has supply voltage (1.5V) and termination voltage (0.75V) generated by the synchronous buck converter TPS51116. And has reference voltage (0.75V) generated by a voltage divider.

    In DM814x datasheet we have:

    8.13.4.2 DDR3 Routing Specifications
    8.13.4.2.4.11 VREFSSTL_DDR Routing
    VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the DDR3 1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 μF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing congestion.

    8.13.4.2.4.12 VTT
    Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is expected to source and sink current, specifically the termination current for the ADDR_CTRL net class Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power sub-plane. VTT should be bypassed near the terminator resistors.

    I can also provide you the below links:

    https://e2e.ti.com/support/dsp/davinci_digital_media_processors/int-dm814x/f/720/t/186456.aspx

    These are for AM3x device, but should be similar for DM814x device:

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/245867.aspx

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/166493.aspx

    http://processors.wiki.ti.com/index.php/AM335x_Schematic_Checklist#General_DDR_guidelines

    http://processors.wiki.ti.com/index.php/AM335x_board_bringup_tips#DDR_configuration

    Regards,
    Pavel

  • Hi Pavel,

    Thank you for the information!  I'm still a bit confused on this since I'm not very familiar with the DM814x.  Could you clarify a bit more on the reason behind why the the DDR3 uses the 0.75V reference voltage from the voltage divider instead of the VTT_REF from the TPS51116?  Is it because the TPS51116 is alredy being used for the supply voltage (1.5V) and termination voltage (0.75V)?  Thank you for your help.

    Best Regards,

    Chuchen Wang

  • Hi Chuchen,

    VREF (reference voltage) and VTT (termination voltage) are different: VREF is a threshold voltage level reference used by the data receiving devices, and VTT is a low impedance current source/sink which is used to terminate the signals.  Although the two are nominally the same voltage they are not the same and care needs to be taken so that any noise on VTT is not cross coupled into VREF.

    Regards,
    Pavel

  • Chuchen,

    Additional information from the Mistral support team:

    DDR VREF could be generated by below two ways & both have own advantages. We have given both the options in DM814x EVM to implement it.
     
    1. For Low capacitance load (fewer than four DDR components), connect VDDQ to VSSQ through a simple resistor divider made up of two equivalent 1kΩ resistors, each with ±1 percent tolerance. Resistor divider with balanced bypassing helps to ensure that VREF is kept midway between VDDQ and VSSQ even in the presence of transients.
     
    2. For High capacitance load (four or more components), regulator IC configured to output 0.75V on VREF will be used.  It minimizes DC error caused by the load current of multiple device input leakage.

    Regards,
    Pavel
  • Thank you Pavel!