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GPMC Question

Baptiste D.
Prodigy 50 points

Sir,

My question is on the  OMAP35x GPMC. OMAP35x have eight independent GPMC chip-selects (gpmc_ncs0 to gpmc_ncs7)  available in the first quarter (Q0) to access NOR/NAND flash and SRAM memories.

The chip-selects have a programmable start address and programmable size (16Mbytes, 32Mbytes, 64Mbytes, or 128Mbytes) in a total memory space of 1Gbyte.

The maximum supported memory size: 256 MBytes.

Can I address 4 x 256MB nand-memory via CS0,CS1,CS2 and CS3 and use total memory space ?

I understand that the CS size (32MB ...) is use for "mirror address".

Best regards

  • 0
    TI__Expert 7210 points

    Baptiste,

    The GPMC chip select ranges are more applicable to NOR flash and asynchonous memories than to NAND.

    Nand storage is not memory mapped into the OMAP’s unified memory space.  Therefore NAND storage is not limited by the GPMC chip select address range.  In fact, the GPMC address lines are not even used for a nand interface.   

    Instead, the nand driver/nand file system resolves nand file block addresses to physical nand address info and commands necessary to access the data in the raw array ( it also handles ECC, wear-leveling and other high level functions).  When the nand driver accesses the GPMC it is actually performing async reads/writes to command, data and address latches on the device via GPMC data and control lines.  Depending upon nand organization, the address info may go out in several words.  In that way, the addressable capacity of the NAND is not limited by the GPMC address range.   In that respect it’s analogous to a disk drive in operation.

     

    So for example, it is possible to access a 512MB nand device on a single GPMC chip select.

     

    Hope this information is useful

     

    DMS