We are configuring a 16 bpp lcd panel. The display is very close to looking perfect, we have a few artifacts that are mucking it up.
I had thought our dts file was looking good, but running fbset has made me second guess that.
If I change clock-frequency, hactive, or vactive and reboot I can see those changes have an affect. However every time I run fbset gives me the following:
mode "640x480-0"
# D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
geometry 640 480 640 480 16
timings 0 0 0 0 0 0 0
accel true
rgba 5/11,6/5,5/0,0/0
endmode
I'm concerned the following lines don't appear to have values set:
# D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
timings 0 0 0 0 0 0 0
I'm thinking this might be a clue to the source of our artifacts, should I be concerned about? Or am I on the wrong path?
Thanks
Below is the section from the dts file, I can include the whole dts file if needed.
device tree
panel {
compatible = "tilcdc,panel";
pinctrl-names = "default";
pinctrl-0 = <&jamex_lcd_pins>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <16>;
fdd = <0x80>;
tft-alt-mode = <0>;
stn-565-mode = <0>;
mono-8bit-mode = <0>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
invert-pxl-clk;
};
display-timings {
native-mode = <&timing0>;
timing0: 640x480-63 {
hactive = <640>;
vactive = <480>;
hback-porch = <46>;
hfront-porch = <97>;
hsync-len = <2>;
vback-porch = <33>;
vfront-porch = <11>;
vsync-len = <2>;
clock-frequency = <40000000>;
hsync-active = <1>;
vsync-active = <0>;
};
};
};
