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Behavior of NAND POP with R/nB->GPMC_WAIT0 not tied high

John F.
Intellectual 830 points
Other Parts Discussed in Thread: OMAP3530

Hello,

Our OMAP3530 board possibly has its POP NAND R/nB line routed incorrectly and it looks like it is not tied high as recommended in the Micron datasheet and as done on the BeagleBoard and I assume 3530EVM.  How would the GPMC behave if this line were floating?  I've tried to retrieve the NAND's ID and it is always 0x00 instead of the expected 0x2C (for Micron).

 

Thanks,

John

  • 0
    TI__Guru 64510 points

    The OMAP3530 does have a pullup on gpmc_wait0 internally which is enabled after reset.  This is indicated in the OMAP3530 datasheet in Table 2-1.  Look at the BALL RESET REL. STATE, which indicates what the state of the pin is after reset has been released.

    However, if your design has gpmc_wait0 routed to other things on the board without an external pullup resistor, the internal pullup will not have enough strength to handle this.

    Do you have access to the gpmc_wait0 signal to try an external pullup?

  • 0 in reply to BrandonAzbell
    Intellectual 830 points

    The gpmc_wait0 line is routed to a nearby BGA and would be tricky to rework, but I'll have a look at the trace layout.  Maybe there's a via that can be used.

     

    Thanks,

    John

  • 0 in reply to John F.
    Intellectual 830 points

    Our hardware engineer discovered that the problem was the unconnected CLE line which feeds-through the CPU for the CBC version of the package.  With this line routed to the GPMC_WAIT0 on the board (and still without an external pull-up), NAND works fine.