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ti8148 nor flash boot problem

qiuxicj MESSN
Intellectual 760 points

Hello, all 

    In my costomer board of ti8148 project, I use a 1Gb nor flash(in the EVM board the size of nor flash is 512Mb). Considering the pinmux I used for GPMC is changed, I change the array used in nor_pad_config_mux(). Am I right?

After that, I built the u-boot and generated the u-boot.bin file following the u-boot user guide(which is fit for nor flash) . And  then I loaded the u-boot.bin to the nor flash correctly.  When I boot from nor flash(of course, I have changed the bootmode), the output from console terminal is :CCCCCCCC.

    Is there any mistakes in my steps?

    How can I solve this problem?Is there any user guide to referenced?

    Any comments and suggestions is welcome! 

    Best Regards, 

    qiuxicj

  • 0
    Intellectual 760 points

    I have changed the pin of GPMC_A6-A14, does this influence to the CPU load code from Nor flash to the Mem. If the answer is yes, how to solve the problem?

  • 0
    Intellectual 760 points

    Hello, all

          I have found something useful about GPMC setting In ti8148 TRM  《4.7.2.2 Pins Used for NOR Boot：Table 4-10. Pins Used for NOR Boot>.But in my project, the HW setting about GPMC addr pin is following:

    a1           mmc2_dat[3]
    a2           mmc2_dat[2]
    a3           mmc2_dat[1]
    a4           mmc2_dat[0]
    a5           vout1_g_y_yc[1]

    a6          gmii0_gtxclk
    a7          gmii0_txd[0]
    a8          gmii0_txd[1] 
    a9          gmii0_txd[2]
    a10        gmii0_txd[3] 
    a11        gmii0_txd[4]
    a12        gmii0_txd[5]

    since the HW setting can not be changed, are there any method to solve the problem?

    Best Regards,

    qiuxicj

  • 0 in reply to qiuxicj MESSN
    TI__Guru**** 170625 points

    Hi Qiuxicj,

    As you are moving from 16-bit non muxed 64MB (512Mb) NOR Flash to 16-bit non muxed 128MB (1Gb) NOR Flash, I think you should also configure the GPMC_A[26] address line (which is not used in the 64MB case).

    See http://processors.wiki.ti.com/index.php/DM81xx_NOR_APPLICATION_NOTES

    2) ROM boot loader does initialization to access only the first 4 KB of the NOR device. The U-Boot start up code has to configure the higher address lines to access the entire NOR device.

    NOR Flash uses the following pins/signals

    GPMC_A0 to A27 [ Based on the NOR size]

    In case of DM81xx NOR boot, ROM boot loader code would configure only the following pins

    GPMC_A0 to A11

    Higher address lines A12 to A27 are not configured by the NOR code. This puts limitation on the amount of memory accessible by the ROM Boot loader code. Since, only the lines A0-A11 are configured, ROM bootloader could  address only the first 4 KB of NOR Device. Hence, the remaining lines have to be initalized by the u-boot boot loader software.

    Interfacing DM814x with various daughter boards

    Interfacing with catalog board

    NOTE:

    1. Since the NOR flash is 16 bit, address line A0 is not used.

    2. Since the NOR flash is 64 MByte, only the address lines a0-a25 are used. A26 and A27 are not used - in your case NOR flash is 128MByte, thus A26 is used!

    3. A27 line is actually used as a GPIO pin to enable the higher address lines. As seen from the schematics(DM814x Base Board + Catalog Board), A27 is connected to the GPIO1-22 pin of DM814x.

    4. Some of the NOR functionalities are available on multiple pins. The pins used by the NOR flash(catalogue board) in such cases are shown  highlighted .

    Software Changes

      Once the PAD control register values are obtained (As described above),  following files have to be modified with this information.

    DM814x Software changes

    Flash Writer Source code

    a) nor-flash-writer/src/device.c

    The structure "nor_pad_cfg" contains pad configuration for catalog board. This has to be modified with the PAD control values for the respective daughter board

    u-boot source code

    a) arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S

    The address lines A12-A27[Line no 341-371of lowlevel_init.S ] have to be modified with PAD control values for the respective daughter board. By default, it is configured for catalog board

    b) board/ti/ti8148/evm.c

    The structure "nor_pad_cfg" contains pin mux configuration for catalog board. This has to be modified with PAD control values for the respective daughter board.

    Linux

    a) arch/arm/mach-omap2/devices.c

    The function "ti814x_nor_init()" configures the pin mux for catalog board. This has to be modfied with PAD control values for the respective daughter board.

    Check also the DM814x Silicon Errata, Advisory 3.0.33 XIP Boot: High-Order Address Handling (GPMC_A[27:13] Pins)

    Regards,
    Pavel