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Hi, all
I work on DM8127, in our application, we use VP->IPIPEIF->ISIF->IPIPEIF->RSZ, VP input is 1920x1088, and output is the same.
1. ISP_ISIF_INT_0 and ISP_RSZ_INT_DMA enabled.
2. RSZ interrupt times is double of INT interrupt.
I want to know, why cause the problem, and how to set correctly.
richard
Richard,
Did you mean that you get RSZ_INT_DMA interrupt 2 times the ISP_ISIF_INT interrupt?
Are you using the IPNC RDK software stack or your own software?
Regards
Rajat
Hi, Rajat,
I re-write many RDK components, Partly reference RDK framework, in our application we discard unused modules, for resizer, we resize 4MP to 5MP resolution, data flow is VP->IPIPEIF->ISIF->IPIPE->RSZ->DDR, when run the application I find ISP_ISIF_INT interrupt as our frame input, but RSZ_INT_DMA only half of our frame input.
CCD module input 25fps, ISIF interrupts 25 times, but RSZ only interrupts 12.5 times.
Following is my IPIPEIF,ISIF,IPIPE,and RSZ setting.
/*
* Description:- Configures Ipipe-if test parameters, ISIF i/p is from PP and ipipe i/p is from ISIF,
* PP -> ipipe-if-> ISIF -> ipipe-if-> ipipe.
*/
ISP_RETURN drvIpipeifSetup( void )
{
ipipeif_path_cfg_t cfg;
cfg.isif_inpsrc = IPIPEIF_ISIF_INPSRC_PP_RAW;
cfg.isif_ip_cfg.pp_ip.dpc1_cfg = NULL;
cfg.isif_ip_cfg.pp_ip.vd_polarity = 0;
cfg.isif_ip_cfg.pp_ip.hd_polarity = 0;
cfg.isif_ip_cfg.pp_ip.int_sw = IPIPEIF_START_POS_PP_VD;
cfg.isif_ip_cfg.pp_ip.align_sync = 0;
cfg.isif_ip_cfg.pp_ip.ini_rsz = 0;
cfg.isif_ip_cfg.pp_ip.ip_clk_sel = IPIPEIF_IP_CLK_VPORT;
cfg.ipipe_inpsrc = IPIPEIF_IPIPE_INPSRC_ISIF;
cfg.ipipe_ip_cfg.isif_ip.avg_filter_enable = AVGFILT_OFF;
cfg.ipipe_ip_cfg.isif_ip.gain = 512;
cfg.ipipe_ip_cfg.isif_ip.YUV16 = YCBCR_16_BIT_DATA;
cfg.ipipe_ip_cfg.isif_ip.YUV8 = YUV8_YUV16;
cfg.ipipe_ip_cfg.isif_ip.YUV8P = YUV8P_C_EVEN_Y_ODD;
cfg.ipipe_ip_cfg.isif_ip.dpc1_cfg = NULL;
cfg.ipipe_ip_cfg.isif_ip.decimation_enable = IPIPEIF_FEATURE_DISABLE;
cfg.ipipe_ip_cfg.isif_ip.resize = 16;
cfg.ipipe_ip_cfg.isif_ip.vd_polarity = 0;
cfg.ipipe_ip_cfg.isif_ip.hd_polarity = 0;
cfg.ipipe_ip_cfg.isif_ip.int_sw = IPIPEIF_START_POS_ISIF_VD;
cfg.ipipe_ip_cfg.isif_ip.align_sync = 0;
cfg.ipipe_ip_cfg.isif_ip.ini_rsz = 0;
return ipipeif_config(&cfg);
}
/* Setup IPIPE, Ignore all functions */
ISP_RETURN drvIpipeSetup( int h_size, int v_size )
{
ipipe_src_cfg_t src;
ISP_RETURN retval = ISP_SUCCESS;
src.wrt = 0;
src.io_pixel_fmt = IPIPE_YCRCB_INPUT_YCRCB_OUTPUT;
src.Even_line_Even_pixel = IPIPE_PIXEL_COLOUR_R;
src.Even_line_Odd_pixel = IPIPE_PIXEL_COLOUR_GR;
src.Odd_line_Even_pixel = IPIPE_PIXEL_COLOUR_GB;
src.Odd_line_Odd_pixel = IPIPE_PIXEL_COLOUR_B;
src.dims.hps = 0;
src.dims.hsz = h_size;
src.dims.vps = 0;
src.dims.v_size = v_size;
retval |= ipipe_config_input_src(&src);
return retval;
}
ISP_RETURN drvIsifSetup( int h_size, int v_size )
{
isif_ip_src_cfg_t cfg;
isif_sdram_op_cfg_t sdram;
ISP_RETURN retval = ISP_SUCCESS;
cfg.sync_enable = ISIF_HD_VD_ENABLE;
cfg.ip_pix_fmt = ISIF_DATA_INPUT_MODE_YUV16;
cfg.data_polarity = ISIF_DATA_NORMAL;
cfg.field_pol = ISIF_POSITIVE_POLARITY;
cfg.hd_pol = ISIF_POSITIVE_POLARITY; // ISIF_NEGATIVE_POLARITY/ISIF_POSITIVE_POLARITY;
cfg.vd_pol = ISIF_POSITIVE_POLARITY; // ISIF_NEGATIVE_POLARITY/ISIF_POSITIVE_POLARITY;
cfg.field_dir = ISIF_SIGNAL_DIRECTION_INPUT;
cfg.hd_vd_dir = ISIF_SIGNAL_DIRECTION_INPUT;
cfg.hd_width = h_size;
cfg.vd_width = v_size;
cfg.ppln_hs_interval = 0;
cfg.lpfr_vs_interval = 0;
cfg.yc_in_swap = ISIF_YCINSWAP_DISABLE;
cfg.msb_inverse_cin = ISIF_MSB_INVERSE_CIN_DISABLE;
cfg.ip_data_msb_pos = ISIF_GAIN_MSB_BIT15;
cfg.field1_pixel_pos[0] = ISIF_COLOR_POSITION_R_YE;
cfg.field1_pixel_pos[1] = ISIF_COLOR_POSITION_GR_CY;
cfg.field1_pixel_pos[2] = ISIF_COLOR_POSITION_GR_G;
cfg.field1_pixel_pos[3] = ISIF_COLOR_POSITION_B_MG;
cfg.field0_pixel_pos[0] = ISIF_COLOR_POSITION_R_YE;
cfg.field0_pixel_pos[1] = ISIF_COLOR_POSITION_GR_CY;
cfg.field0_pixel_pos[2] = ISIF_COLOR_POSITION_GR_G;
cfg.field0_pixel_pos[3] = ISIF_COLOR_POSITION_B_MG;
cfg.cfa_pattern = ISIF_CFA_PATTERN_MOSAIC;
cfg.r656_inferface_mode = ISIF_REC656IF_MODE_DISABLE;
cfg.err_correction_mode = ISIF_ERR_CORRECTION_FVC_DISABLE;
cfg.ccir656_bit_width = ISIF_BW656_DISABLE;
/* SDRAM configuration */
sdram.sdram_hpos = 0;
sdram.sdram_hsize = h_size; /* Image width */
sdram.sdram_vpos0 = 0;
sdram.sdram_vpos1 = 0;
sdram.sdram_vsize = v_size; /* Image height */
sdram.memory_addr_decrement = ISIF_HLINE_ADDR_INCREMENT;
sdram.memory_addr_offset = h_size * 2;
/* Field offset */
sdram.field_offset_params.fid_polarity = ISIF_FID_NO_CHANGE;
sdram.field_offset_params.odd_field_line_offset = ISIF_FIELD_LINE_OFFSET_PLUS_1;
sdram.field_offset_params.even_line_even_field_offset = ISIF_LINE_OFFSET_PLUS_1;
sdram.field_offset_params.odd_line_even_field_offset = ISIF_LINE_OFFSET_PLUS_1;
sdram.field_offset_params.even_line_odd_field_offset = ISIF_LINE_OFFSET_PLUS_1;
sdram.field_offset_params.odd_line_odd_field_offset = ISIF_LINE_OFFSET_PLUS_1;
sdram.memory_addr = 0;
sdram.alias_filter_enable = ISIF_LPF_ANTI_ALIAS_DISABLE;
sdram.dpcm_predictor = ISIF_DPCM_ENCODE_PREDICTOR2;
sdram.dpcm_enable = ISIF_DPCM_ENCODER_ENABLE_OFF;
sdram.ccd_raw_shift_value = ISIF_CCD_DATA_NO_SHIFT;
sdram.ccd_field_mode = ISIF_CCD_MODE_NON_INTERLACED; /* Progressive */
sdram.wen_selection_mode = ISIF_NO_WEN;
sdram.data_write_enable = ISIF_DATA_WRITE_DISABLE; /* ISIF_DATA_WRITE_ENABLE/ISIF_DATA_WRITE_DISABLE */
sdram.msb_inverse_cout = ISIF_MSB_INVERSE_COUT_DISABLE;
sdram.sdram_byte_swap = ISIF_BYTE_SWAP_DISABLE;
sdram.y_position = ISIF_SELECT_Y_POS_EVEN_PX;
sdram.sdram_ext_trig = ISIF_NO_EXTRG;
sdram.sdram_trig_select = ISIF_SDRAM_TRGSEL_DWEN_REG;
sdram.ccd_valid_log = ISIF_WENLOG_SIGNAL_LOGICAL_AND_INTERNAL;
sdram.fid_detection_mode = ISIF_FID_LATCH_VSYNC;
sdram.yc_out_swap = ISIF_YCOUTSWAP_DISABLE;
sdram.sdram_pack_fmt = ISIF_SDRAM_PACK_16BITS;
sdram.vsync_enable = ISIF_VLDC_RESYNC_VSYNC_ENABLE;
/* Culling */
sdram.culling_params.horizontal_odd_culling = 0xFF;
sdram.culling_params.horizontal_even_culling = 0xFF;
sdram.culling_params.vertical_culling = 0xFF;
retval |= isif_config_pol(&cfg);
retval |= isif_config_input_src(&cfg);
retval |= isif_config_sdram_format(&sdram);
retval |= isif_config_vd0_line_number(v_size-5);
return retval;
}
ISP_RETURN drvRszSetup( int in_h_size, int in_v_size )
{
rsz_yc_min_max val;
rsz_common_cfg_t cfg;
rsz_global_crop_dims_t crop;
ISP_RETURN retval = ISP_SUCCESS;
/* Set common configuration */
cfg.ip_port = RSZ_IP_IPIPEIF; /* RSZ_IP_IPIPE/RSZ_IP_IPIPEIF */
cfg.wrt_enable = RSZ_WRT_DISABLE; /* RSZ_WRT_DISABLE/RSZ_WRT_ENABLE */
cfg.rszA_dma_size = 0;
cfg.rszB_dma_size = 0;
cfg.fifo_thr_low = 0;
cfg.fifo_thr_high = 0;
cfg.rsz_pix_fmt_mode = YUV422_IP_YUV420_OP;
cfg.yuv_phase = RSZ_YC_COSITED;
cfg.rszA_int_lines = 0;
cfg.rszB_int_lines = 0;
cfg.fracdiv = 65535;
retval |= rsz_common_config(&cfg);
ISP_SET32(rsz_reg->SRC_FMT0, CSL_RSZ_SRC_FMT0_BYPASS_OFF, CSL_RSZ_SRC_FMT0_BYPASS_SHIFT, CSL_RSZ_SRC_FMT0_BYPASS_MASK);
ISP_SET32(rsz_reg->GCK_SDR, CSL_RSZ_GCK_SDR_CORE_ON, CSL_RSZ_GCK_SDR_CORE_SHIFT, CSL_RSZ_GCK_SDR_CORE_MASK);
/* Set global crop */
crop.h_pos = 0;
crop.h_size = in_h_size;
crop.v_pos = 0;
crop.v_size = in_v_size;
retval |= rsz_cfg_global_crop(&crop);
/* Set Y/C throsheld */
val.y_min = 0;
val.c_min = 0;
val.y_max = 254;
val.c_max = 254;
retval |= rsz_cfg_yc_max_min(&val);
return retval;
}
Thanks.
Richard
