LCDC interrupts stop after indeterminate amount of time

Dinesh Balasubramaniam

Other Parts Discussed in Thread: OMAPL138, AM1808, OMAP-L138, DA8XX

I have an OMAP L138 based system that uses the Davinci-PSP-SDK-03.22.00.02. The system runs a graphics application. After an indeterminate period of time (order of single digit minutes) the image seen on the LCD panel gets scrambled i.e. the (0,0) position keeps changing to different positions on the screen.

The clock and sync signals on the interface look correct. Upon further investigation we discovered that the LCD controller stops generating interrupts to the ARM. Any suggestions on what might cause this to happen? Also looking for suggestions on further debugging steps to try.

Thanks,

Dinesh

over 11 years ago

0 Pubesh over 11 years ago

TI__Mastermind 20790 points

Dinesh,

I understand that, you are using OMAPL138 based custom board and Graphics LCD.
The liquid crystal display controller (LCDC) is used to interface to character display panels for text message display or to graphical display panels for image/video display.
Easily extend application to include visual capabilities.

Go to LogicPD's web site. Click on the Kit Contents tab, at the bottom of the page click at:
Am1808 SOM-M1 GEL, CCS Setup, & BSL Files - you will need to create an account in their website if you do not have one already and download the files.
The basic graphics lcd example will be at:
BSL_test_code_LogicPd_OMAP-L138\ARM eXp Graphics LCD Test\src

Please have a look at the below wiki,
http://processors.wiki.ti.com/index.php/StarterWare_LCDC
http://processors.wiki.ti.com/index.php/StarterWare_LIDD
http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.22.00.02_Device_Driver_Features_and_Performance_Guide
http://processors.wiki.ti.com/index.php/DaVinci_PSP_03.22.00.02_Release_Notes

0 Dinesh Balasubramaniam over 11 years ago in reply to Pubesh

Intellectual 480 points

Hi Pubesh,

Thanks for the reply. Looks like you got the posts reversed when writing your answer :) Posting your reply at the end of this thread for future reference. Answers and additional questions below.

1. LCD controller runs in raster mode.

2. Where in the linux kernel do I increase the priority of the LCDC master? I tried modifying the entry corresponding to the LCD in array da850_default_priorities defined in arch/arm/mach-davinci/da850.c

[IRQ_DA8XX_LCDINT] = 7,

but the values in this array are written to the AINTC registers, not the SYSCFG registers.

3. I'm using the drivers provided in TI's SDK. This sets up the palette and writes 0x4000 followed by all zeros.

Thanks,

Dinesh

Reply from yesterday

LCDC Modes:

1. Raster Mode
2. LIDD Mode (Character LCD)
http://processors.wiki.ti.com/index.php/StarterWare_01.10.01.01_User_Guide
Which mode are you using?

LCDC Debugging:
1. Increase LCDC master priority in SYSCFG to prevent FIFO underruns
2. Ensure that the Palette is placed at the Frame Buffer base address
3. When using 12- and 16-BPP modes, which don’t require a Palette, a 32 byte Palette of value 4000h followed by all 0s must still be used

0 Dinesh Balasubramaniam over 11 years ago in reply to Dinesh Balasubramaniam

Intellectual 480 points

LCDC priority should be written to register MSTPRI2 (pg 243 in http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf).

This register is not defined in the kernel used for the OMAP L138, at least not for the da8xx. To raise the priority of the LCDC follow the steps below:

Add address of MSTPRI2 to arch/arm/mach-davinci/include/mach/da8xx.h

#define MSTPRI2_REG 0x118

Do a read/modify/write of this register where appropriate (in your board init file or the driver for the LCDC)

p = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG));

__raw_writel(pri & 0x1fffffff, DA8XX_SYSCFG0_VIRT(DA8XX_MSTPRI2_REG));

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LCDC interrupts stop after indeterminate amount of time