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some question about CACHE on C674x DSP Megamodule of OMAP L137

arthur14426
Intellectual 420 points
Other Parts Discussed in Thread: OMAP-L137

Hi all, I have some question about L1P cache.

1. 

The  SPRUFK5.pdf(  TMS320C674x DSP MegamoduleReference Guide )  describe that L1P memory is divided into two regions (denoted L1P region 0 and L1P region 1)  and the size of region 1 is less than the size of  region 0.  But what's the essential difference between them and which register control the size of the two region ?

And I also read SPRS563B.pdf (OMAP-L137 Low-Power Applications Processor) .  The doc show a memory map ,  DSP L1P RAM is mapped to two region (0x00E0 0000 --- 0x00E0 7FFF  and 0x11E0 0000 --- 0x11E0 7FFF ) , and I wander whether the two differnce zone denote the two diffence region?

2.

SPRUFK5.pdf(  TMS320C674x DSP MegamoduleReference Guide )  describe that L1P architecture allows the size of L1P cache to be selected at run time by L1PCFG Register . Can L1P be split  into 16K SRAM and 16K cache simultaneously? If the case is practical , where  is the SRAM mapped ? In this mode . How does C674x core fetch the ins package?( L1 SRAM ---> L!P RAM ---> core    or   L1 SRAM ---> core directly?  )

 

  • 0
    TI__Mastermind 24340 points

    arthur said:
    The  SPRUFK5.pdf(  TMS320C674x DSP MegamoduleReference Guide )  describe that L1P memory is divided into two regions (denoted L1P region 0 and L1P region 1)  and the size of region 1 is less than the size of  region 0

    Not sure why you say that region 1 is smaller than region 0. Each region can have up to 16K.

    arthur said:
    But what's the essential difference between them and which register control the size of the two region ?

     L1P was broken in two regions so you can have flexibility. See on the page 24 of the TMS320C674x DSP Megamodule Reference Guide :

    "1. Each region may have a different number of wait-states.

     2. Each region has separate memory protection entries"

    The control register are described on section 2.6 of the same document.

    Wait states are not configurable by software, see page 25 section 2.3.1.3.

    For memory protection Registers please see section 2.9.2.

    arthur said:
    And I also read SPRS563B.pdf (OMAP-L137 Low-Power Applications Processor) .  The doc show a memory map ,  DSP L1P RAM is mapped to two region (0x00E0 0000 --- 0x00E0 7FFF  and 0x11E0 0000 --- 0x11E0 7FFF ) , and I wander whether the two differnce zone denote the two diffence region?

     0x00E0 0000 --- 0x00E0 7FFF  - Is the address that can only be accessed by the DSP core.

    0x11E0 0000 --- 0x11E0 7FFF - Is the address that will be used by EDMA and peripherals to access that part of memory (and the ARM will use this address to for OMAP-L137)

    Both addresses point to the same physical part of the memory. 

    arthur said:
    Can L1P be split  into 16K SRAM and 16K cache simultaneously?

    Yes.

    arthur said:
    If the case is practical , where  is the SRAM mapped ?

     For example, if you have 16K of SRAM, and 16K of cache, then the first 16K will go to SRAM and the last will go to cache.

     

  • 0 in reply to Mariana
    Intellectual 420 points

    Mariana, thank u


    Mariana said:

    Not sure why you say that region 1 is smaller than region 0. Each region can have up to 16K.

    section 2.3.1.1 of SPRUFK5.pdf say "The size of region 1 must be less than or equal to the size of region 0, when region 0 is enabled." ....... When region 0 is 0K bytes, its memory protection pages go unused.
    But I could not find which register to enable/disable region 0/1 and the size of each.I wander ,with respect to L137 ,whether the region 0/1 is fix size ,that's to say first 16KB is for region 0 , and the second for region 1 ?