AM3874 EDMA3 constant mode

Hi Michi,

Michi Yama said:

My customer is trying to use EDMA3 with constant addressing mode. 

Which AM3874 peripheral module you are reading/writing with the EDMA3 controller in CONST mode?

Michi Yama said:

Does anyone know whether the EDMA3 of AM3874 has some issues, or not?

AM387x TRM states that both INCR and CONST EDMA3 address modes are supported. And in AM387x Silicon Errata, I can not find any bug related to the EDMA3 CONST addressing mode. We have only Advisory 3.0.79 — EDMA: TC0 and TC1 Read Accesses Always Use Physical Address which is not related to the EDMA3 CONST mode.

In AM387x TRM, we have the below restriction when using EDMA3 in CONST addressing mode, you should be align with:

8.4.3.2.2 Channel Source Address (SRC)
The 32-bit source address parameter specifies the starting byte address of the source. For SAM in increment mode, there are no alignment restrictions imposed by EDMA3. For SAM in constant addressing mode, you must program the source address to be aligned to a 256-bit aligned address (5 LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 8.4.12.3 for additional details.

8.4.3.2.3 Channel Destination Address (DST)
The 32-bit destination address parameter specifies the starting byte address of the destination. For DAM in increment mode, there are no alignment restrictions imposed by EDMA3. For DAM in constant addressing mode, you must program the destination address to be aligned to a 256-bit aligned address (5 LSBs of address must be 0). The EDMA3TC will signal an error, if this rule is violated. See Section 8.4.12.3 for additional details.

8.4.3.8 Constant Addressing Mode Transfers/Alignment Issues

8.4.12.3 Error Generation
Errors are generated if enabled under three conditions:
• EDMA3TC detection of an error signaled by the source or destination address.
• Attempt to read or write to an invalid address in the configuration memory map.
• Detection of a constant addressing mode TR violating the constant addressing mode transfer rules (the
source/destination addresses and source/destination indexes must be aligned to 32 bytes).

Either or all error types may be disabled. If an error bit is set and enabled, the error interrupt for the
concerned transfer controller is pulsed.

The registers/bits related to the EDMA3 CONST addressing mode are:

OPT[10:8] FWID - FIFO Width. Applies if either SAM or DAM is set to constant addressing mode.
       [1] DAM - Destination address mode
       [0] SAM - Source address mode.

ERRSTAT[2] TRERR - Transfer request (TR) error event.

SAOPT[10:8] FWID - FIFO Width. Applies if either SAM or DAM is set to constant addressing mode.
       [1] DAM - Destination address mode
       [0] SAM - Source address mode.

DFOPTn[10:8] FWID - FIFO Width. Applies if either SAM or DAM is set to constant addressing mode.
       [1] DAM - Destination address mode
       [0] SAM - Source address mode.

See also the below E2E threads:

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/165045.aspx

http://e2e.ti.com/support/arm/sitara_arm/f/791/t/226226.aspx

Regards,
Pavel

Dear Pavel-san,

Thank you for your support.

Our customer's status is the following.

The source of module of DMA transfer is NAND flash. And the destination module of DMA transfer is DDR3.

Customer did DMA  transfer without TC0MMU, and it is transfered to the physical address of DDR3 memory.

This transfer is done on Windows compact 7 OS.  As to the limitation of WEC7, OS reads out the data that is transfered by DMA from the logical address of DDR3. For this reason, the cache coherency of AM3874 is not kept, and DMA transfer failed.

So customer tried to do DMA transfer with TC0MMU. This means MMU is enabled and the data is transfered to the logical address of DDR3, and the cached coherency is kept.

But the result was bad. DMA transfer is not done by T0MMU enabled.

What is the wrong?

Please give me advice.

Best regards,

Michi

Michi,

Michi Yama said:

The source of module of DMA transfer is NAND flash. And the destination module of DMA transfer is DDR3.

You are using the AM3874 GPMC module to connect the NAND flash, right? And the transfer is from NAND flash to DDR3, NAND flash using CONST mode, DDR3 using INCR mode, right?

Michi Yama said:

So customer tried to do DMA transfer with TC0MMU. This means MMU is enabled and the data is transfered to the logical address of DDR3, and the cached coherency is kept.

But the result was bad. DMA transfer is not done by T0MMU enabled.

I think you hit the SiliconErrata (see below). Do you also think so?

http://www.ti.com/lit/er/sprz345c/sprz345c.pdf

Advisory 3.0.79 EDMA: TC0 and TC1 Read Accesses Always Use Physical Address

Revision(s) Affected: 3.0 and earlier

Details:   The EDMA transfer controllers (TC0 and TC1) are intended to support either physical addressing, or virtual addressing. The EDMA addressing mode is configured with the Control Module MMU_CFG register TC0MMU and TC1MMU bit fields.

Physical addressing is the default configuration and is used in most systems. This addressing uses the direct path between each TC through the L3 interconnect to the target memory or peripheral. The Physical addressing mode works as expected.

Virtual addressing is accomplished via the System MMU. When enabled for Virtual addressing, the EDMA virtual address accesses should loop-back through the L3 interconnect through the System MMU and again through the L3 interconnect (now with Physical Address) to the target memory or peripheral. The TC0 and TC1 write accesses behave as expected and use the MMU virtual:physical translation path. However, the TC0 and TC1 read accesses do not go through the MMU and always use the Physical address; therefore, TC0 and TC1 read cannot be used with virtual addresses.

Workaround: None. Virtual addressing cannot be supported for EDMA read accesses.

Best regards,
Pavel

Dear Pavel-san,

Thank you for your quick reply.

I would like to confirm one thing of this errata you pointed out.

This errata says the TCx read access is not supported with virtual address.  Does  this "read access" mean that it is forward to system MMU module of AM3874 internal? Or does it mean it is forward to the system memory (DDR3 and so on)?  Customer try to write  to DDR3 memory from NAND flash by DMA transfer. This is write access, not read access. ( I looked Figurre 1-8 of TRM).

I am confused.

Please advise me again.

Best regards,

Michi

Michi,

Michi Yama said:

Does  this "read access" mean that it is forward to system MMU module of AM3874 internal? Or does it mean it is forward to the system memory (DDR3 and so on)?

By design the path of the read/write access is:

1 case, when MMU_CFG[ ] TCxMMU = 0: EDMA -> L3 -> DDR3

2 case, when MMU_CFG[ ] TCxMMU = 1: EDMA -> L3 -> MMU -> L3 -> DDR

The write access has no issues.

But the read access has silicon bug and does not work as by design. The path of the read access is the same when TCxMMU = 0 or 1, it is always: EDMA ->L3 ->DDR3

Regards,
Pavel

Dear Pavel-san,

Thank you for your support.

I would like to reconfirm.

In case of the DMA transfer with MMU:

Source : NAND flash  ---------->  Destination :  DDR3

EDMA reads the data from NAND with MMU  ------ N.G.

EDMA writes the data to DDR3 with MMU ---- Work

Is my understanding right?

Best regards,

Michi

Michi,

Yes, I understand the same as you.

The read path through the system MMU is broken! While the read path from EDMA directly to NAND (without going through the system MMU) works fine.

The write path (from EDMA to DDR3) works fine for both cases: directly and through the system MMU.

Regards,
Pavel