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Configuring L3 firewall on a OMAP5432 uEVM GP board.

Sander Bogaert
Prodigy 55 points

Hi,

I was wondering if it's supposed to be possible to write directly to the memory mapped L3 firewall configuration registers? I have some code trying to do so in order to set them up but without results. I checked if my code is correct by using a debugger and placing watchpoints on the correct memory addresses. A write just seems to be ignored. Am I missing something? This is on a OMAP5432 uEVM GP board.

Regards,

Sander

  • 0
    TI__Mastermind 29520 points

    Hello Sander,

    I would suggest to check your PRCM configuration. Maybe L3 clock configuration is not set.

    Check the clock signals for following Clock domains:

    CD_L3_MAIN2  - includes modules - GPMC, L3_MAIN_2 interconnect
    CD_L3_INSTR  - includes modules - L3_MAIN_3 interconnect, L3_INSTR interconnect, OCP_WP_NOC

    CD_L3_MAIN1 - L3_MAIN_1 interconnect

    Check CM_CORE_AON clock generator if L3_ICLK is enabled.

    Best regards,

    Yanko

  • 0 in reply to Yanko Todorov-XID
    Prodigy 55 points

    Hi Yanko,

    I've been going through the manual and I'm still unsure which registers you'd want me to check. I did however dump the CM_CLKSEL_CORE register ( 0x4A004100 ) and verified L3_ICLK is enabled ( content was 0x00000110 ).

    Since I'm using the UART I guess the L4 interconnect is operational. I use u-boot and since the DRAM is connected to the L3 ( EMIF1 EMIF2 ) I suspect L3 should be working too?

    Could you give some more insight on where to check the clock settings? Am I wrong in thinking L3 and L4 must be enabled since I'm using the features mentioned above?

    Best regards,

    Sander

  • 0 in reply to Sander Bogaert
    TI__Mastermind 29520 points

    Hello Sander,

    To check your clock signals configuration use the clock tree tool - OMAP543x Clock Tree Tool (v1.9.0.8)

    This is the easy way to observe if your clock domains are not enabled and to see possible problems with L3, L4 clock.

    Other option which you must check the PWRSTCTRL registers in following power PRM Instances:

    L3INIT_PRM,

    OCP_SOCKET_PRM, 

    CKGEN_PRM

    COREAON_PRM

    CORE_PRM

    Best regards,

    Yanko

  • 0 in reply to Yanko Todorov-XID
    Prodigy 55 points

    Hi Yanko,

    I've been experimenting with the board and after a while I figured out some things weren't activated. After setting some registers I now read the following values:

    Name Address Value
    CM_CLKSEL_CORE 0x4a004100 0x0000 0110
    PM_L3INIT_PWRSTCTRL 0x4ae07600 0x000f 0204
    PM_CORE_PWRSTCTRL 0x4ae06700 0x03ff 0f07
    CM_L3INSTR_L3_MAIN_3_CLKCTRL 0x4a008e20 0x0000 0001
    CM_L3INSTR_L3_INST_CLKCTRL 0x4a008e28 0x0000 0001
    CM_L3INSTR_OCP_WP_NOC_CLKCTRL 0x4a008e40 0x0000 0001
    CM_L3INIT_HSI_CLKCTRL 0x4a009638 0x0004 0001

    I still can't seem to write to the firewall registers in order to define a region etc.. there must still be something missing. Any ideas?

    Kind regards,

    Sander

  • 0 in reply to Sander Bogaert
    TI__Mastermind 29520 points

    Hello Sander,

    Could you explain in what regions do you try to write?

    Probably you try to write in protection regions. Refer to section 14.2.3.8.3.3 Protection Mechanism per Region Examples in OMAP5432 TRM and see the described example.

    See registers - CONTROL_SEC_ERR_STATUS_DEBUG and CONTROL_SEC_ERR_STATUS_FUNC in the Control Module.

    Best regards,

    Yanko