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OFF Mode related register dump time

jacob tao
Prodigy 20 points

Hi all

    I have faced a problem that my smps2(VDD_CORE_L) did not ramp down to 0V while device suspend. MPU & IVA can ramp  to 0V properly.                          

   First I check if my device entered OFF MODE. So I dumped the related register RM_L3_1_L3_1_CONTEXT[1]. Context has no change. What means that the device did not enter off mode.

   I printed out the log info. Which shown that PD_CORE and PD_L4_PER did not hit targeted status.

log msg:

[  109.423065] pmu2 -- Powerdomain (core_pwrdm)  target state OSWR (achieved=ON current=ON saved=ON)
[  109.423065] pmu2 -- Powerdomain (gfx_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (abe_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (dss_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (tesla_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (emu_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (ivahd_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (cam_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (l3init_pwrdm)  target state OSWR (achieved=OSWR current=OSWR saved=OSWR)
[  109.423065] pmu2 -- Powerdomain (l4per_pwrdm)  target state OSWR (achieved=ON current=ON saved=OSWR)
[  109.423065] pmu2 -- Powerdomain (cefuse_pwrdm)  target state OFF (achieved=OFF current=OFF saved=OFF)
[  109.423065] pmu2 -- Powerdomain (mpu_pwrdm)  target state OSWR (achieved=OFF current=ON saved=ON)

     Then I dump all the clock domain related registers.  But I find out that I don't know what is the time to dump these registers. Cause the status changed during off mode transition. It it proper to dump these register before calling cpu_suspend(). 
Thanks for you reply
BRS
jacob
  • 0
    TI__Mastermind 29520 points

    Hello Jacob,

    Sorry for delayed answer.

    The VDD_CORE_L is switch off - when the PRCM module then deassert the signal system clock request to the SCRM, if so configured by the software. Similarly, it deasserts the signal power request if configured by software.
    If power request signal is used for VDD_CORE_L management, then VDD_CORE_L is ramped down to 0V.

    My suggestion is to observe OFF mode sequence described in section 3.9.3.1 Device Off Mode Sleep Sequence

    Unfortunately there is not information about dumping time of PRCM registers.

    Best regards,

    Yanko