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C6748 : Timer P0-12 and undesired interrupt event

Benjamin CHAUVEL
Prodigy 20 points
Other Parts Discussed in Thread: TMS320C6748

Hello,

I'm facing a problem with the use of timer Timer64P0 - 12.

it's set as a 32 bit unchained timer. The other timer 34 remains in reset all time.

For my little test, i'm using the timer 12 in run once mode. I set the PRD to 10 for example then i release the reset.

When TIM12 reaches 10. the PRDINTSTAT12 field in the INTCTLSTAT register is set. That's okay, and as the PRDINTEN12 field is set to 0, i should not get any interrupt.

But the EVTFLAG0, bit EF4 is set which corresponds to the EVT# 4 which is the T64P0_TINT12 interrupt.

The problem also comes from the field INTSEL4 in the INTMUX1 register as the reset value is 4 : the default source is already the timer Timer64P0 - 12.

As the corresponding bit in IER register is not set, the interrupt is not served. But i don't understand why the IFR logs the interrupt as the interrupt is disabled at timer level. If i change the INTMUX1 value, of course the event is not bound to INT4 and the IFR bit is not set to 1 so my question is about the PRDINTEN12 field.

I attached a little example project to show how I'm testing this.

Thanks.

Benjamin.

TestEventINT.zip
  • 0
    TI__Mastermind 20790 points

    Benjamin,

    Welcome to the TI E2E forum. I hope you will find many good answers here
    In addition you can find some details through the TI.com documents and the TI Wiki Pages.
    Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    The timers can be used as per below,
    Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
    One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers)

    Signal Name: TM64P0_IN12
    Interrupt Name: T64P0_TINT12 (Timer64P0 - TINT12) or T64P0_TINT34 (Timer64P0 Interrupt 34)
    Timer Mode: Dual 32-bit unchained general-purpose timer mode
    Operation Mode: One-time operation (timer runs for one period then stops)
    Clock Source: Internal or External clock(event input via timer input pins)?

    When the timer counter matches the timer period, a maskable timer interrupt (TINT12)
    and a timer EDMA (TEVT12) are generated.

    The timers can be configured as a dual 32-bit unchained timers by setting the TIMMODE
    bit to 1 in TGCR.

    When the timer is enabled for one time operation (ENAMODEn = 1), it counts up until the counter
    value equals the period value and then stops.

    Please can you verify the PRDINTSTAT12 register value?
    Kindly have a look at TMS320C6748 TRM for unchained mode config.

     

  • 0 in reply to Pubesh
    Prodigy 20 points

    The PRDINTSTAT12 is set to 1.

    But I've found my problem : i was missing the PLUSEN set to 1 in the TGCR. With that the PRDINTEN12 does control the interrupt generation.