2Gb NAND, Xloader and address cycle

Shobhraj Singh

Hello.

It seems like the 2Gb NAND addressing scheme followed by the xloader is mildly different from the well known 5 cycle addressing scheme.

Typically, the GPMC is expected to push out in the:

1st cycle => CA7 - CA0 (A7 - A0)

2nd cycle => CA11 - CA8 (A11-A8)

3rd cycle =>BA7 BA6 PA5..PA0 (A19-A12)

4th cycle => BA15 - BA8 (A27 - A20)

5th cycle => BA16 (A28)

The 1st and second address cycles indicate the offset within the page, the PAx bits indicate the page within a block and the BAx bits indicate the block number.

The xloader seems to do this differently in NanD_Address(...).

1st cycle => CA7 - CA0 (A7-A0)

2nd cycle => CA10 - CA8 (A10-A8)

3rd cycle => BA6 PA5..PA0 CA11 (A18-A11)

4th cycle => BA14 - BA7 (A26-A19)

5th cycle => BA16-BA15 (A27)

The main difference seems to be the way in which the page size is being treated. Xloader considers page size as 2048 byts as against the spec (2048 + 64 = 2112 bytes) (Micron-Tech Note 29-19 on NAND flash).

Is this tech note generic or plainly specific to micron products?

Best regards,

over 16 years ago

0 Shobhraj Singh over 16 years ago

Prodigy 140 points

Please find next the xloader code snippet written for the K9f1G device:

static int NanD_Address(unsigned int numbytes, unsigned long ofs)
{
    uchar u;

     NAND_CTL_SETALE(NAND_ADDR);

    if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE
                || numbytes == ADDR_OOB)
    {
        ushort col = ofs;

        /*SS => Cycle - 1 : A7:A0 - Correct*/
        u = col & 0xff;
        WRITE_NAND_ADDRESS(u, NAND_ADDR);

        /* SS comments ->Cycle - 2 : A10-A8 */
        /*
        * A x8 device has 2112 columns while a x16 device has 1056 columns.
        *
        * Column address pertaining to start of spare area is:
        * x8 device = 2048 (A11 = 1, A10-A0 = 0)
        * x16 device = 1024 (A10 = 1, A9-A0 = 0)
        *
        */
        u = (col >> 8) & 0x07;
        if (numbytes == ADDR_OOB)
            u = u | ((bus_width == 16) ? (1 << 2) : (1 << 3));
        WRITE_NAND_ADDRESS(u, NAND_ADDR);
    }

    if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE
                || numbytes == ADDR_OOB)
    {
        /* SS => Violation Violation Cycle-3 : A18-A11 , should have been A19-A12 */
        u = (ofs >> 11) & 0xff;
        WRITE_NAND_ADDRESS(u, NAND_ADDR);

        /* SS => Violation Violation Cycle-4 : A26 - A19, should have been A27-A20 */
        u = (ofs >> 19) & 0xff;
        WRITE_NAND_ADDRESS(u, NAND_ADDR);

        /* SS comments => Violation Violation Cycle - 5 : A31 : A27, should have been A28 and above*/
        /* One more address cycle for devices > 128MiB */
        if (chipsize > (128 << 20)) {
            u = (ofs >> 27) & 0xff;
            WRITE_NAND_ADDRESS(u, NAND_ADDR);
        }
    }

     NAND_CTL_CLRALE(NAND_ADDR);

     NAND_WAIT_READY();
    return 0;
}

Page-10 of the data sheet at

http://www.digchip.com/datasheets/download_datasheet.php?id=1089382&part-number=K9F1G08R0A

lists the address cycle.

Clearly xloader is piping out A11 twice? Why shouldnt this be a problem?

Best regards,

Processors

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2Gb NAND, Xloader and address cycle