How to make McBSP3 FSX to output signal?

user5970223

Other Parts Discussed in Thread: DM3730

Hi all!

I am developing a driver for Android on DM3730. I want to use McBSP3_FSX to output a frame synchronization signal. In the section 21.4.3.2 of DM3730, it's said that I can set McBSP3MCBSPLP_PCR_REG[10] FSRM bit =1, McBSP3.MCBSPLP_PCR_REG[11] FSXM = 1, McBSP3.MCBSPLP_SRGR2_REG[12] FSGM=1, McBSP3.MCBSPLP_SPCR2_REG[6] GRST bit=1 and McBSP3.MCBSPLP_SPCR2_REG[7] FRST
bit=0 to make McBSP3.FSX to output a synchronization signal. But I get nothing after I do as above.

I don't know the reason of this problem. Is it true that I can't set McBSP3.FSX to output signal? Or I set a wrong mode for McBSP3? I need help. Thank you!

John

over 11 years ago

0 Cvetolin Shulev-XID over 11 years ago

TI__Guru 65405 points

Hi Johnny,

All settings which you point out are correct. If we consider that there aren't problems with the hardware and pinmux configuration I'll need of the whole McBSP configuration to verify the issue.

Tsvetolin Shulev

0 user5970223 over 11 years ago in reply to Cvetolin Shulev-XID

Prodigy 240 points

Hello Mr. Shulev.

Glad to see your reply.

In my program, I configuration McBSP3 with the source below:

struct omap_mcbsp_reg_cfg mcbsp_cfg = {
    .spcr1 = RJUST(0) | DXENA | RINTM(2),
    .spcr2 = FREE | SOFT | XINTM(2) | XSYNC_ERR | GRST,
    .pcr0 = FSXM| FSRM | CLKXM | CLKRM | CLKRP | FSXP,
    .rcr1 = RFRLEN1(0) | RWDLEN1(0),
    .rcr2 = RPHASE | RFRLEN2(0) | RWDLEN2(0) | RCOMPAND(0) | RDATDLY(0),
    .xcr1 = XFRLEN1(0) | XWDLEN1(0),
    .xcr2 = XPHASE | XFRLEN2(0) | XWDLEN2(0) | XCOMPAND(0) | XDATDLY(0),
    .srgr1 = FWID(3) | CLKGDV(186),
    .srgr2 = FSGM | FPER(3),
    };
        si3217x_dev->mcbsp_id = OMAP_MCBSP3;
        status = omap_mcbsp_request(si3217x_dev->mcbsp_id);
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
        mdelay(1);
        mcbsp_cfg.srgr2 |= GSYNC;
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
        mdelay(1);
        mcbsp_cfg.spcr1 |= RRST;
        mcbsp_cfg.spcr2 |= XRST;
        mcbsp_cfg.spcr2 ^= FRST;    //Clear FRST
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
        mcbsp_cfg.spcr2 |= FRST;    //set FRST
        mcbsp_cfg.spcr2 |= GRST;
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);

Before the code above, I set pinmux in u-boot/board/ti/beagle/beagle.h with the code below:

        MUX_VAL(CP(MCBSP3_DX),          (IDIS  | PTD | DIS | M0)) /*PCM_DX*/\
        MUX_VAL(CP(MCBSP3_DR),          (IEN | PTD | DIS | M0)) /*PCM_DR*/\
        MUX_VAL(CP(MCBSP3_CLKX),        (IEN | PTD | DIS | M0)) /*PCM_CLKX*/\
        MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M0)) /*PCM_SYNC*/\

I'm not sure whether there are some other configuration of pins will conflict with this. And I can set or clear PCR.FSXP to toggle the polarity of FSX. Then I think the pinmux of FSX should be correct, isn't it? Additional, I had make success to set CLKX to output signal already. Does this mean the pinmux is right?
Please help me to check these code. Thank you!

BR

John.

0 Cvetolin Shulev-XID over 11 years ago in reply to user5970223

TI__Guru 65405 points

Hi John,

The pinmux configuration is correct. About McBSP registers configuration could you dump their values after setting the posted configuration. I would like to see what exactly is set.

Tsvetolin Shulev

0 user5970223 over 11 years ago in reply to Cvetolin Shulev-XID

Prodigy 240 points

Hi Shulev,

The dump function I wrote is as following:

void DumpMcBSP_cfg()
{
    printk(KERN_ALERT "spcr1=%x", mcbsp_cfg.spcr1);
    printk(KERN_ALERT "spcr2=%x", mcbsp_cfg.spcr2);
    printk(KERN_ALERT "pcr0=%x", mcbsp_cfg.pcr0);
    printk(KERN_ALERT "rcr1=%x", mcbsp_cfg.rcr1);
    printk(KERN_ALERT "rcr2=%x", mcbsp_cfg.rcr2);
    printk(KERN_ALERT "xcr1=%x", mcbsp_cfg.xcr1);
    printk(KERN_ALERT "xcr2=%x", mcbsp_cfg.xcr2);
    printk(KERN_ALERT "srgr1=%x", mcbsp_cfg.srgr1);
    printk(KERN_ALERT "srgr2=%x", mcbsp_cfg.srgr2);
}

This function is called like following:

        si3217x_dev->mcbsp_id = OMAP_MCBSP3;
        status = omap_mcbsp_request(si3217x_dev->mcbsp_id);
        DumpMcBSP_cfg();
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
        mdelay(1);
        mcbsp_cfg.srgr2 |= GSYNC;
        DumpMcBSP_cfg();
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
        mdelay(1);
        mcbsp_cfg.spcr1 |= RRST;
        mcbsp_cfg.spcr2 |= XRST;
        mcbsp_cfg.spcr2 &= (0xffff ^ FRST);    //Clear FRST
        DumpMcBSP_cfg();
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
        mcbsp_cfg.spcr2 |= FRST;    //set FRST
        mcbsp_cfg.spcr2 |= GRST;
        DumpMcBSP_cfg();
        omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);

The output of dumping is:

<1>spcr1=a0
<1>spcr2=368
<1>pcr0=f09
<1>rcr1=0
<1>rcr2=8000
<1>xcr1=0
<1>xcr2=8000
<1>srgr1=3ba
<1>srgr2=1003

------------------------------------------------------------------------
<1>spcr1=a0
<1>spcr2=368
<1>pcr0=f09
<1>rcr1=0
<1>rcr2=8000
<1>xcr1=0
<1>xcr2=8000
<1>srgr1=3ba
<1>srgr2=9003

---------------------------------------------------------------------------------
<1>spcr1=a1
<1>spcr2=369
<1>pcr0=f09
<1>rcr1=0
<1>rcr2=8000
<1>xcr1=0
<1>xcr2=8000
<1>srgr1=3ba
<1>srgr2=9003

---------------------------------------------------------------------------
<1>spcr1=a1
<1>spcr2=3e9
<1>pcr0=f09
<1>rcr1=0
<1>rcr2=8000
<1>xcr1=0
<1>xcr2=8000
<1>srgr1=3ba
<1>srgr2=9003
For convenient of reading, I insert a dividing line between every calling. Please check it to help me. Thank you!

John.

0 user5970223 over 11 years ago in reply to Cvetolin Shulev-XID

Prodigy 240 points

Hi Shulev,

I think my problem is really a tiny issue. But I can't resolve it for 2 months. Could you be kind to help me more? That will be determinal to me. Thank you!

John

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How to make McBSP3 FSX to output signal?