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DM8148 DDR3 MT41J128M16

enson Steven
Intellectual 630 points

We had designed an DM8148 Board with two 16-bit DDR3 Memory Device (Micron MT41K128M16JT-125 ) connected to both DDR controllers(DDR0,DDR1).

And I test the DDR in ccs, then in 300MHz,333MHz,533MHz, test was passed.But at 400MHz,it appeared to read error.I modify the ddr following the guied TI814x-DDR3-Init-U-Boot.pdf,but nothing changed.

I change the 8148_evm.gel to this

#define DDR3_EMIF_TIM1_DEFINE_400 0x0AAAE4DB
//#define DDR3_EMIF_TIM2_DEFINE_400 0x682F7FDA
#define DDR3_EMIF_TIM2_DEFINE_400 0x68437FDA //by ensonking
//#define DDR3_EMIF_TIM3_DEFINE_400 0x501F82BF
#define DDR3_EMIF_TIM3_DEFINE_400 0x501F83FF //by ensonking
//#define DDR3_EMIF_REF_CTRL_DEFINE2_400 0x00000C30
#define DDR3_EMIF_REF_CTRL_DEFINE2_400 0x00000C35 //by ensonking
//#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_400 0x61C011B2
#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_400 0x61C012A3 //by ensonking
#define DDR3_EMIF_READ_LATENCY_DEFINE_400 0x00173209


Does anyone have experience about this?


B&R

Enson

  • 0
    TI__Guru**** 170625 points

    Enson,

    In the GEL file available from the http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot wiki (TI814x_ddr3.gel), we have:

    //DDR3 400 MHz - CL=6,CWL=5
        #define DDR3_EMIF_TIM1_DEFINE_400            0x0AAAD4DB
        #define DDR3_EMIF_TIM2_DEFINE_400            0x682F7FDA
        #define DDR3_EMIF_TIM3_DEFINE_400            0x501F82BF
        #define DDR3_EMIF_REF_CTRL_DEFINE2_400            0x00000C30
        #define DDR3_EMIF_SDRAM_CONFIG_DEFINE_400        0x61C011B2
        #define DDR3_EMIF_DDRPHYCR_DEFINE_400            0x00170209

    hotmenu DDR3_EMIF0_EMIF1_400MHz_Config()
        {
            GEL_TextOut("\t ****  Configuring DDR PLL to 400 MHz......... \n");
            cmdDDRPLL(CLKIN,19,800, 2);
            GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration in progress......... \n");
            cmd_DDR3_EMIF0_EMIF1_Config(DDR3_EMIF_DDRPHYCR_DEFINE_400,DDR3_EMIF_TIM1_DEFINE_400,
            DDR3_EMIF_TIM2_DEFINE_400,DDR3_EMIF_TIM3_DEFINE_400,DDR3_EMIF_REF_CTRL_DEFINE2_400,
            DDR3_EMIF_SDRAM_CONFIG_DEFINE_400);
            GEL_TextOut("\tDM814x DDR3 EVM EMIF0 and EMIF1 configuration is DONE. \n");    
        }

    Do you have errors if you use the default DDR3/400MHz settings?

    Note also that DMM LISA MAP registers are programmed as:

    /*Program the DMM to Access EMIF0 and EMIF1*/
            WR_MEM_32(DMM_LISA_MAP__0, 0x80600100);
            WR_MEM_32(DMM_LISA_MAP__1, 0x80600100);
            WR_MEM_32(DMM_LISA_MAP__2, 0xC0600200);
            WR_MEM_32(DMM_LISA_MAP__3, 0xC0600200);
                
            while(RD_MEM_32(DMM_LISA_MAP__0)!=0x80600100);
            while(RD_MEM_32(DMM_LISA_MAP__1)!=0x80600100);
            while(RD_MEM_32(DMM_LISA_MAP__2)!=0xC0600200);
            while(RD_MEM_32(DMM_LISA_MAP__3)!=0xC0600200);

    While for 512MB settings (256MB to DDR0 and 256MB to DDR1), you should be aligned with the below settings:

    http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map#Changing_Memory_Map_For_512MB_DM814x_Board

    Regards,
    Pavel