HDVICP Processing logic clock source selection

Hi Davide Bonfanti,

1. I don't think there is is a must and should rule about the frequency of HDVICP and DDR. But it is up to your intelligence to get optimal performance with available hardware and frequency range. I saw few use cases where  freqency of HDVICP and DDR are not same.
2. If you see the PLL module in ARM  guide of DM36X,  input clk dividers for DDR and HDVICP are not unique. They are different modules. That means physically it is routed via different path. But, yes you can program it in such a way that, you get same frequency for both HDVICP and DDR.
3. This is optional. It depends on your OSC frequency, and the output frequency what you want.  Just to answer the question, Yes You can.

Hi ravikiran,
Thank you for the answer.
My question wasn't if it is possible to have both ARM and HDVICP connected to the same pll output, but if it is correct since they have different allowed maximum frequencies.
For instance, in 300MHz part number, maximum arm freq is 297MHz and max HDVICP is 270MHz.
Using the settings I found in dvsdk (inside ubl code) both arm and HDVICP are set to work at 297MHz.

I would like to have a feedback to understand if I've catched everything properly (and so I have to modify my ubl, since there is no public repository for it) or if I'm missing something.

Thanks

Davide Bonfanti,

To be more clear on the comments what I have made,  ARM frequency and HDVICP freq need not be one and the same. This  is up to the developer to make proper utilization  of the available clock & clock domains. Only constrain is HDVICP clk can't be  more than ARM clk.

Since you have access to device.c file, refer ARM297_DDR243_OSC24 use case as an example, which is tested + working use case where ARM clocked  @ 297 while HDVICP @ 243. Also there are some other use cases, where, HDVICP freq & DDR clocks are operating at different freq.

Hope it clarify your doubt.

ravikiran,

I don't want to bother you, but just reading device.c file I can argue:
 there is no  ARM297_DDR243_OSC24 section, but ARM297_DDR270_OSC24 one and I can use it.
In this session I can find: 

#define PLL1_MUL                0x2d  
#define PLL1_PREDIV             0x3
#define PLL1_POSTDIV            0x0     //PLL1 output ( 0x2d * 2* 24 / (0x3+ 1) = 540 MHZ )
        
#define PLL1_DIV1               0x2c    //USB 12 MHZ
#define PLL1_DIV2               0x1     // POST DIV 540/2 -> HDVICP max =270 MHZ 
#define PLL1_DIV3               0x1     // POST DIV 540/2  -> MJCP/HDVICP  max =270 MHZ 
#define PLL1_DIV4               0x3     // POST DIV 540/4  -> EDMA/EDMA CFG     MAX =135 MHZ 
#define PLL1_DIV5               0x1     // POST DIV 540/2 -> VPSS       max =270 MHZ
#define PLL1_DIV6               0x13    // 27Mhz POST DIV 540/20  -> VENC 27 MHZ        
#define PLL1_DIV7               0x0     // POST DIV 540/2 -> DDR max =270 MHZ
#define PLL1_DIV8               0x05    // POST DIV 540/6 -> 90 MMC0/SD0 <=100
#define PLL1_DIV9               0x1     // POST DIV 540/2 -> CLKOUT


#define PLL2_MUL                0x63
#define PLL2_PREDIV             0x7
#define PLL2_POSTDIV            0x0     //PLL2 Output (0x63 * 2 * 24 / (0x7 + 1) = 594MHZ

#define PLL2_DIV1               0x18    // 594/25 23.6 MHZ USB
#define PLL2_DIV2               0x1     // 594/2 =297 Mhz -> ARM 
#define PLL2_DIV3               0x1     // 297 MHZ 2 * ddr
#define PLL2_DIV4               0x1c    // POST DIV 594/29 = 20.48 -> VOICE
#define PLL2_DIV5               0x07    // POST DIV 594/8 = 74.25 ->VIDEO HD

#define PERIPHERAL_CLK_CTRL_VAL 0x243F04FC

#define DDR_FREQ         270

As I can argue, since PERIPHERAL_CLK_CTRL_VAL has both bit(26) & bit(29) set, both ARM and HDVICP are connected to the second output of the second PLL, that is they work at the same frequency (297MHz) and, for HDVICP, this is an overclock, since in the datasheet it is written that it cannot go faster than 270MHz.

Is this right or not?

Davide Bonfanti,

Yes you are right. There seems to be some issue  ARM297_DDR270_OSC24 use case.
Instead you can set 26th bit of PERIPHERAL_CLK_CTRL_VAL to 0.