Hi,
According to csl documentation CACHE_invL1d and CACHE_wpL1d work only on pointers and sizes aligned to cache line size. That is the minimum memory block that can be synced is 128 bytes. This might potentially lead to memory corruption.
I am worried about sending and receiving IPC messages through MessageQ using shared memory transport. Suppose I allocated memory for a message through MessageQ_allocate and wrote some data. The shared memory block will be cached in L1. Now suppose message arrives and is placed next to the allocated block. Cache invalidate must be called for the arrived message memory block. If it happens that a part of the outgoing message that was not yet send and a part of arrived message reside in the same cache line region then the outgoing message will be corrupted. I looked through messageq implementation and it seems that all messages are allocated from the same heap and there is no mechanism to ensure that they are aligned on cache line boundary.
Is this a valid concern or I don't understand something about MessageQ IPC?
Thank you,
Alexey