Hi~
I'm using DM368 and porting PLCD. now I have DCLK, VSYNC, HSYNC. but LCD data siganl was long.
It seem's like Hsync. I don't know why? please help me. thanks.
Here is my setting.
Pinmux
/* PRGB */
MUX_CFG(DM365, VCLK, 1, 22, 1, 0, false)
MUX_CFG(DM365, COUT7, 1, 0, 3, 1, false)
MUX_CFG(DM365, COUT6, 1, 2, 3, 1, false)
MUX_CFG(DM365, COUT5, 1, 4, 3, 1, false)
MUX_CFG(DM365, COUT4, 1, 6, 3, 1, false)
MUX_CFG(DM365, COUT3, 1, 8, 3, 1, false)
MUX_CFG(DM365, COUT2, 1, 10, 3, 1, false)
MUX_CFG(DM365, COUT1, 1, 12, 3, 1, false)
MUX_CFG(DM365, COUT0, 1, 14, 3, 1, false)
MUX_CFG(DM365, LCDOUT_HSYNC, 1, 16, 1, 0, false)
MUX_CFG(DM365, LCDOUT_VSYNC, 1, 16, 1, 0, false)
and same place in mux.h
/* PRGB */
DM365_VCLK,
DM365_COUT7,
DM365_COUT6,
DM365_COUT5,
DM365_COUT4,
DM365_COUT3,
DM365_COUT2,
DM365_COUT1,
DM365_COUT0,
DM365_LCDOUT_HSYNC,
DM365_LCDOUT_VSYNC,
static void venc_enabledigitaloutput(struct v4l2_subdev *sd, int benable)
{
struct venc_state *venc = to_state(sd);
struct venc_platform_data *pdata = venc->pdata;
void __iomem *vpss_clkctl_reg;
v4l2_dbg(debug, 2, sd, "venc_enabledigitaloutput\n");
printk("vpbe_venc: venc_enabledigitaloutput \n\r");
vpss_clkctl_reg = DAVINCI_SYSMODULE_VIRT(0x44);
if (benable) {
venc_write(sd, VENC_VMOD, 0);
venc_write(sd, VENC_CVBS, 0);
if (cpu_is_davinci_dm368()) {
enable_lcd();
/* Select EXTCLK as video clock source */
__raw_writel(0x18, vpss_clkctl_reg); // 0x1a //0x08
/* Set PINMUX for GPIO82 */
davinci_cfg_reg(DM365_GPIO82); // DM365_GPIO82
gpio_request(82, "lcd_oe"); // 82
/* Set GPIO82 low */
gpio_direction_output(82, 0);// 82
gpio_set_value(82, 0);
}
venc_write(sd, VENC_LCDOUT, 0);
venc_write(sd, VENC_HSPLS, 0);
venc_write(sd, VENC_HSTART, 0);
venc_write(sd, VENC_HVALID, 0);
venc_write(sd, VENC_HINT, 0);
venc_write(sd, VENC_VSPLS, 0);
venc_write(sd, VENC_VSTART, 0);
venc_write(sd, VENC_VVALID, 0);
venc_write(sd, VENC_VINT, 0);
venc_write(sd, VENC_YCCCTL, 0);
venc_write(sd, VENC_DACSEL, 0);
} else {
venc_write(sd, VENC_VMOD, 0);
/* disable VCLK output pin enable */
venc_write(sd, VENC_VIDCTL, 0x141);
/* Disable output sync pins */
venc_write(sd, VENC_SYNCCTL, 0);
/* Disable DCLOCK */
venc_write(sd, VENC_DCLKCTL, 0);
venc_write(sd, VENC_DRGBX1, 0x0000057C);
/* Disable LCD output control (accepting default polarity) */
venc_write(sd, VENC_LCDOUT, 0);
if (pdata->venc_type != DM355_VPBE)
venc_write(sd, VENC_CMPNT, 0x100);
venc_write(sd, VENC_HSPLS, 0);
venc_write(sd, VENC_HINT, 0);
venc_write(sd, VENC_HSTART, 0);
venc_write(sd, VENC_HVALID, 0);
venc_write(sd, VENC_VSPLS, 0);
venc_write(sd, VENC_VINT, 0);
venc_write(sd, VENC_VSTART, 0);
venc_write(sd, VENC_VVALID, 0);
venc_write(sd, VENC_HSDLY, 0);
venc_write(sd, VENC_VSDLY, 0);
venc_write(sd, VENC_YCCCTL, 0);
venc_write(sd, VENC_VSTARTA, 0);
/* Set OSD clock and OSD Sync Adavance registers */
venc_write(sd, VENC_OSDCLK0, 1);
venc_write(sd, VENC_OSDCLK1, 2);
}
}
static int venc_set_prgb(struct v4l2_subdev *sd,
struct vpbe_enc_mode_info *mode_info)
{
struct venc_state *venc = to_state(sd);
struct venc_platform_data *pdata = venc->pdata;
v4l2_dbg(debug, 2, sd, "venc_set_prgb\n");
printk("vpbe_venc: venc_set_prgb");
#if 1
/* Setup clock at VPSS & VENC for SD */
if (pdata->setup_clock(VPBE_ENC_CUSTOM_TIMINGS, CUSTOM_TIMING_320_240) < 0)
{
printk("venc_set_prgb Setup_clock error");
return -EINVAL;
}
/* setup pinmux */
if (pdata->setup_pinmux(pdata->if_params, 0) < 0)
{
printk("venc_set_prgb setup_pinmux error");
return -EINVAL;
}
venc_enabledigitaloutput(sd, 1);
venc_write(sd, VENC_VIDCTL, 0x141);
/* set VPSS clock */
vpss_enable_clock(VPSS_VPBE_CLOCK, 1);
vpss_enable_clock(VPSS_VENC_CLOCK_SEL, 1);
venc_write(sd, VENC_DCLKCTL, 0x3); // 2
venc_write(sd, VENC_DCLKPTN0, 0x2); //
/* Set the OSD Divisor to 1. */
venc_write(sd, VENC_OSDCLK0, 0x00); // 0
venc_write(sd, VENC_OSDCLK1, 0x01); // 1
/* Clear composite mode register */
venc_write(sd, VENC_CVBS, 0);
/* DM365 pinmux */
venc_write(sd, VENC_CLKCTL, 0x11);
/* Set VIDCTL to select VCLKE = 1,
VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 */
venc_modify(sd, VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
VENC_VIDCTL_VCLKE);
venc_modify(sd, VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
VENC_VIDCTL_VCLKZ);
venc_modify(sd, VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
VENC_VIDCTL_SYDIR);
venc_modify(sd, VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
VENC_VIDCTL_YCDIR);
// venc_write(sd, VENC_VIDCTL, 0x2000); //
venc_modify(sd, VENC_DCLKCTL,
1 << VENC_DCLKCTL_DCKEC_SHIFT, VENC_DCLKCTL_DCKEC);
venc_write(sd, VENC_DCLKPTN0, 0x1);
venc_set_display_timing(sd, mode_info);
venc_write(sd, VENC_SYNCCTL,
(VENC_SYNCCTL_SYEV |
VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL
| VENC_SYNCCTL_VPL));
/* Configure VMOD. No change in VENC bit */
venc_write(sd, VENC_VMOD, 0x2011);
venc_write(sd, VENC_LCDOUT, 0x1);
if (cpu_is_davinci_dm368()) {
/* Turn on LCD display */
mdelay(200);
gpio_set_value(82, 1);
}
}