TI C667x experts-
In an HP DL380 server with a DSPC-8681E (quad) card, running exhaustive tests for robustness, we see intermittent memory read/write errors with the A103 version of the card. Here is a problem description and notes:
1) The test program writes two (2) random memory locations with random 32-bit data and then reads these locations back. Each access is 32-bits (no block accesses in this test). L2 cache is disabled.
2) Errors do not occur:
-with A101 version cards
-with shared mem (MCSRAM)
3) Errors occur:
-with L2SRAM and DDR3 mem
-only on core0 of each C6678 device
-only on lower 16 bits of read-back values
-more often with a 1 GHz C667x clock rate.
A 1.25 GHz clock rate completely removes
errors from core0 of DSP0, but there are still
errors with core0 of DSPs 2-3. Errors are
always worse on DSP3
It's possible this is a PCIe vs. C667x timing issue, as they run on different clocks, which could be affected by PCIe bridge priority in the PLX chip card (with DSP3 being last), or even physical placement and trace length of the devices on the card.
What tests can we run to affect PCIe timing? Can we change C667x PCIe register settings? Any ideas on how to shine more light on this problem welcome. We've tried various server BIOS settings, such as disabling C-states, enabling PCIe 1.0 transaction rate, and changing x86 CPU clock rate.
Thanks.
-Jeff
Signalogic
