McBSP working, RRDY not getting enabled

Sujan Nag1

Prodigy 190 points

Other Parts Discussed in Thread: DM3730

Hello,

The environment is: Embest devkit8500 which has a DM3730 processor.

linux kernel: 2.6.32

To test the McBSP interface, I wanted to perform a simple loopback test.

The McBSP 1 pins are coming to the connector.

My requirements are:

Short DX and DR pin to perform a loopback(externally).
provide clock to the CLKR from CLKX(internally),
provide framesync FSR from FSX(internally).

Well, the CLKX and FSX seems to be configured correctly, (Verfied by probing the CLKX and FSX pins)

Also I was able to check the FSR and CLKR pins and they had similar waveform to FSX and CLKX as expected.

I am sending data 0x0F0F, from the transmitter, and I am also able to see the data on the Oscilloscope.

But the RRDY bit never goes high.

Here are my configuration parameters:

config->xccr |= (XDMAEN | DXENDLY(1));
config->xcr1 |= (XWDLEN1(2) | XFRLEN1(0));
config->rcr1 |= (RWDLEN1(2) | RFRLEN1(0));
config->pcr0 |= (CLKRM | FSRM | FSXM | CLKXM );
config->srgr2 |= (FSGM | FPER(15));
config->srgr1 |= (CLKGDV(25) | FWID(2));

Also the control_devconf0 register is configured:

static void __iomem *DEVCONF0;

DEVCONF0 = (u32 *)ioremap(OMAP343X_SCM_BASE+CONTROL_DEVCONF0, 1);
if(DEVCONF0 == NULL)
{
printk(KERN_ALERT "SN: Failed to ioremap %d\n\r",DEVCONF0);
kfree(config);
}

reg_value = readl(DEVCONF0);
reg_value |= 0x00000018;

writel(reg_value,DEVCONF0);

iounmap((void *)DEVCONF0);

udelay(4);

I am using the mcbsp.c file present in arch/arm/plat-omap/mcbsp.c, and in polling mode.

The RRDY bit always stays low. Any suggestions about where I might get wrong.

Any help would be aprreciated.

Thanks

Sujan

over 12 years ago

0 Sujan Nag1 over 12 years ago

Prodigy 190 points

Hello,

The RRDY bit is getting enabled now, I had to configure the CLKX and FSX pin as inputs in the u-boot, as per the TRM. But due to some reason I am still getting a zero in the receiver section.

Are the word length, frame period and frame width parameters okie? Or what are the suggest able parameters if I have to transfer 16 bit data?

Please Suggest.

Thanks

Sujan

0 Sujan Nag1 over 12 years ago in reply to Sujan Nag1

Prodigy 190 points

Hello all,

I am still stuck with the above problem. The linux kernel version used is 2.6.32

I also tried to configure the McBSP interface in DMA mode. But the problem is the same. The DRR register always shows a zero. The FSX and CLKX are working fine(verified using probe). Also the transmitter is able to transmit the Data(probed the DX pin). But the DRR reg is stuck at zero.

Also, there is PMIC 65930 present on the board, which employs McBSP2 for audio. I compared the configuration parameters and they seem to be okie.

Any suggestion regarding the issue would be helpful.

Thanks and Regards

Sujan

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McBSP working, RRDY not getting enabled