Good morning
we would like to know how many clocks are needed for accessing various Sitara memory areas.
Looking into Sitara forum we found that L1 cache requires just 1 clock, internal SRAM about 20 clocks, L3 OCMC0 about 40 clocks. Are these information correct ?
How many cycles are needed for a locked 32kB block of L2 cache ?
How many clocks are added by L3F - L3S for accessing external memory on GPMC ? and on Emif ?
We cannot find this information on TRM spruh73i or anywhere else.
Hoping in your quick reply...
Best regards
Stefano & Mario
