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check ack/nack after slave address

Wang YenCheng
Prodigy 40 points

hi all,

    how can I check the ack/nack after the (S+SlaveAddr+R/W bit)  ??

    what I want is, if I get a nack then I'm going to repeat S+SlaveAddr+R/W again, until I get an ack.

    but I always get XDR irq, even I'v set the OMAP_I2C_BUF_RXFIF_CLR and OMAP_I2C_BUF_TXFIF_CLR to clear both fifo.

    at this step, there doesn't have any data I need to send...so I didn't set the OMAP_I2C_CNT_REG.

    best regards

  • 0
    TI__Guru**** 161600 points

    Hello,

    The ack/nack can be checked by reading I2C_IRQSTATUS[1]NACK bit. When NACK=0  acknowledge signal has been received and we have normal operation. If NACK = 1 no acknowledge has been received and the I2C controller sends an interrupt to the local host (MPU), you need to:
    - clear NACK bit

    - I2C_CON[0]STT (start bit) & I2C_CON[1]STP (stop bit) are cleared by hardware

    - Reprogram I2C registers and check the status registers 

     See block diagrams in Section 23.1.5.1.1.3 Programming Flow Diagrams, figure 23-29 through figure 23-36. 

    You are getting XDR interrupt because you've enabled the I2C draining feature (see section 23.1.4.8.4 HS I2C Draining Feature (I2C Mode Only) in OMAP4460 TRM). If you don't need this you can disable it by clearing I2C_IE[14] XDR_IE & I2C_IE[15] RDR_IE bits.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 40 points

    Hi Yordan Kovachev,

        thanks for your reply, I have other question need your or someone's suggestion~~

        according to the I2C setup procedure in the spec, it says,

        it need to set the I2C_CNT[15:0] before set I2C_CON[0].

        does it mean i2c module will directly start to receive/write data after the S+slaveaddr+R/W+ack/nack sequence ??

        I want set I2C_CNT[15:0] later... I don't need any data transfer at the beginning.

        is it possible separate S+slaveaddr+R/W+ack/nack as first step and receiving/writing data as second step ?

        so I can control them when to work. 

        and I2C_CNT is not allowed 0x0...

  • 0 in reply to Wang YenCheng
    TI__Guru**** 161600 points

    Hi,

    I2C controller in OMAP works as you've written you send Start bit+slaveaddr+R/W+ack+<number of bytes to be read/written according to programming of I2C_CNT register>+STOP bit:

    You cannot separate the i2c protocol in fragments, that is send S+slaveaddr+RW+ack/nack on one pass and then on another to send the data to be read/written.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 40 points

    Hi Yordan Kovache-XID,

        thanks for your reply~

        so, I have to set I2C_CNT before raising a START condition, or in other words,

        raising START condition without setup I2C_CNT is illegal, right ?

  • 0 in reply to Wang YenCheng
    TI__Guru**** 161600 points

    Yes your understanding is correct. This can also be seen in the I2C Programming Flow diagrams: DCOUNT bit field is set in the setup procedure, which takes place before the transfer.

    Best Regards,

    Yordan.

  • 0 in reply to Yordan Kovachev
    Prodigy 40 points

    Hi Yordan Kovachev-XID,

        thank you !! I get it !!