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TCI663x errata: clarification required

Ville Baillie
Genius 3480 points

KeyStoneII.BTS_errata_advisory.2
No ARM boot from NOR Flash over EMIF.
The errata is talking about XIP, execute in place?
 
In the bootloader manual http://www.ti.com/lit/ug/spruhj3/spruhj3.pdf under emif boot -
 

-          The RBL will start reading from the NOR memory

-          at the chip select base address plus

-          the base address offset specified by the boot

-          mode pins. The data will be stored at the

-          address specified in the GP header. It will

-          continue reading GP Header formatted data

-          from the NOR memory and storing it as dire

-          cted by the headers until a complete image

-          has been read. When the complete image has b

-          een read, the RBL will branch to the base

-          address of the last GP data block in the image.

Am I right in thinking the above does not constitute direct execution and that we can use EMIF16 to load sections from Flash to SDRAM, as specified in the GPO header, and branch to SDRAM to start execution as the last GP data block header?

Also…
 
Just noticed that errata 8 http://www.ti.com/lit/er/sprz402/sprz402.pdf is the same as errata 2
With a slightly different title and only affecting revision 1.0

Can anyone provide any clarification?

  • 0
    TI__Guru* 81335 points

    Hi Ville Baillie,

    TCI66xx devices such as TCI663x are supported directly through Local Field Applications Engineers (FAEs.)  These devices are not supported on the E2E forum.  Please contact your local FAE for support of these devices.  If you are not sure who your local FAE is, then please contact your local technical sales representative and they will be able to put you in contact with your local FAE.

    Thanks.

  • 0
    TI__Guru** 116170 points

    Yes, your understanding is correct. Keystone II devices do support ARM booting from NOR flash but Execution in place(XIP) mode is not supported due to inherent limitation of A15 core of performing 64-byte cacheline wrap mode accesses to EMIF. The boot ROM in case of ARM boot will read the NOR boot image as data and copies to device memory for execution instead of executing in place.

    I have reported the errata 8 and errata 2 issue to the literature team.This does appear to be the same.I will get back to you when I get a response on the same

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    TI__Guru** 116170 points

    Advisory. 2  and Advisory 8 are different. Advisory 2 can`t get fixed due to inherent limitation of A15 cache line wrap  while Advisory 8 is ROM boot related issue and has been fixed in PG v1.1.

    Regards,

    Rahul