Hi all!
I am developing a driver for Android on DM3730. I want to use McBSP3_FSX to output a frame synchronization signal. In the section 21.4.3.2 of datasheet of DM3730, it's said that I can set McBSP3MCBSPLP_PCR_REG[10] FSRM bit =1, McBSP3.MCBSPLP_PCR_REG[11] FSXM = 1, McBSP3.MCBSPLP_SRGR2_REG[12] FSGM=1, McBSP3.MCBSPLP_SPCR2_REG[6] GRST bit=1 and McBSP3.MCBSPLP_SPCR2_REG[7] FRST
bit=0 to make McBSP3.FSX to output a synchronization signal. But I get nothing after I do as above.
Before the application running, I set pinmux in u-boot/board/ti/beagle/beagle.h with the code below:
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*PCM_DX*/\ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*PCM_DR*/\ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*PCM_CLKX*/\ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*PCM_SYNC*/\
In my program, I configuration McBSP3 with the source below:
struct omap_mcbsp_reg_cfg mcbsp_cfg = {
.spcr1 = RJUST(0) | DXENA | RINTM(2),
.spcr2 = FREE | SOFT | XINTM(2) | XSYNC_ERR | GRST,
.pcr0 = FSXM| FSRM | CLKXM | CLKRM | CLKRP | FSXP,
.rcr1 = RFRLEN1(0) | RWDLEN1(0),
.rcr2 = RPHASE | RFRLEN2(0) | RWDLEN2(0) | RCOMPAND(0) | RDATDLY(0),
.xcr1 = XFRLEN1(0) | XWDLEN1(0),
.xcr2 = XPHASE | XFRLEN2(0) | XWDLEN2(0) | XCOMPAND(0) | XDATDLY(0),
.srgr1 = FWID(3) | CLKGDV(186),
.srgr2 = FSGM | FPER(3),
};
void DumpMcBSP_cfg()
{
printk(KERN_ALERT "spcr1=%x", mcbsp_cfg.spcr1);
printk(KERN_ALERT "spcr2=%x", mcbsp_cfg.spcr2);
printk(KERN_ALERT "pcr0=%x", mcbsp_cfg.pcr0);
printk(KERN_ALERT "rcr1=%x", mcbsp_cfg.rcr1);
printk(KERN_ALERT "rcr2=%x", mcbsp_cfg.rcr2);
printk(KERN_ALERT "xcr1=%x", mcbsp_cfg.xcr1);
printk(KERN_ALERT "xcr2=%x", mcbsp_cfg.xcr2);
printk(KERN_ALERT "srgr1=%x", mcbsp_cfg.srgr1);
printk(KERN_ALERT "srgr2=%x", mcbsp_cfg.srgr2);
}
si3217x_dev->mcbsp_id = OMAP_MCBSP3;
status = omap_mcbsp_request(si3217x_dev->mcbsp_id);
DumpMcBSP_cfg();
omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
mdelay(1);
mcbsp_cfg.srgr2 |= GSYNC;
DumpMcBSP_cfg();
omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
mdelay(1);
mcbsp_cfg.spcr1 |= RRST;
mcbsp_cfg.spcr2 |= XRST;
mcbsp_cfg.spcr2 &= (0xffff ^ FRST); //Clear FRST
DumpMcBSP_cfg();
omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
mcbsp_cfg.spcr2 |= FRST; //set FRST
mcbsp_cfg.spcr2 |= GRST;
DumpMcBSP_cfg();
omap_mcbsp_config(si3217x_dev->mcbsp_id, &mcbsp_cfg);
The output of dumping is:
spcr1=a0
spcr2=368
pcr0=f09
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=3ba
srgr2=1003
spcr1=a0
spcr2=368
pcr0=f09
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=3ba
srgr2=9003
spcr1=a1
spcr2=369
pcr0=f09
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=3ba
srgr2=9003
spcr1=a1
spcr2=3e9
pcr0=f09
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=3ba
srgr2=9003
Then I can't find anything outputted from McBSP3.FSX. Although this, I can set the polarity of it by set or clear pcr0.FSXP. So I think I am right for configuration of pinmux. I don't know why I can't get output of McBSP3.FSX. Please help me. Thank you!
BR
John
