Other Parts Discussed in Thread: THS8200, OMAP3530, TFP410
Hi:
Our platform is OMAP 3503. THS8200 is used to convert input from OMAP (RGB 24bit) into component 720P YCbCr signal. But it outputs no signal to TV.
To be more accurate, only signal from the Y channel can be detected with scope(but seems to be blanking lines).
The input signals to THS8200 are also connected to the DVI module (TFP41). But the DVI works as well.
The outputs from OMAP are: (The same setting as OMAP3530 EVM)
1. RGB 24 bit, the 2 LSBs for each channel are connected to ground.
2. HSYNC, VSYNC, PCLK, FID (low)
3. The list of Display Controller Registers shows more detail.
The following are THS8200 registers value we set. I also listed the reason why I set such value for each register, based on my understanding of the registers of THS8200 and the OMAP3 display subsystem, which might be misunderstanding though.
I believe I must have set the THS8200 register improperly. I appreciate if anyone can give me the advice on the THS8200 registers setting based on the OMAP3's display setting.
Kevin
THS8200 registers:
reg02: 04
reg03: 01
// 0x04 - 0x19 COLOR SPACE CONVERSION, RGB->YPbPr. Settings copied from the THS8200 datasheet
reg04: 00
reg05: da
reg06: 80
reg07: 78
reg08: 02
reg09: 0c
reg0a: 02
reg0b: dc
reg0c: 81
reg0d: 94
reg0e: 81
reg0f: dc
reg10: 00
reg11: 4a
reg12: 02
reg13: 0c
reg14: 80
reg15: 30
reg16: 00
reg17: 08
reg18: 02
reg19: 01
//0x1a - 0x1b: test control, not used.
reg1a: 00
reg1b: 00
//0x1C input: 30-bit YCbCr/RGB 4:4:4, Interpolation filters before/after the CSC are bypassed,
reg1c: 30
//0x1d - 0x24: amplitudes, copied from the DM6446 sample code
reg1d: ff
reg1e: 49
reg1f: b6
reg20: ff
reg21: ff
reg22: ff
reg23: 13
reg24: 15
// Negative Hsync width (half of total width) 0x18 = 0x30 / 2.
//Setting based on: 0x4805 0464(7:0) [0x30]
// The actual value is 0x31. I dont know how to split it into half. I tried 0x19 as well, but it did not work.
reg25: 18
// End of Active Video to start of negative sync: 0x3F.
//Setting based on: 0x4805 0464(19:8) [0x3e]
reg26: 3f
// positive hsync width (half of total width) 0X18 = 0x30 / 2.
//Setting based on: 0x4805 0464(7:0) [0x30]
reg27: 18
// Distance from negative-to-positive transition of tri-level sync to start of broad pulse (HDTV mode).
// Setting based on: 0x4805 0464(31:20) [0xfe]
reg28: ff
// for SDTV, not HDTV
reg29: 00
//Width of HSYNC to active video: 0xff.
//Setting based on: 0x4805 0464(31:20) [0xfe]
reg2a: ff
//bit [6] and [7] combined with reg28 and reg2a to set the width of HSYNC to active video.
reg2b: 00
// reg 0x2c - 0x2e for SDTV
reg2c: 00
reg2d: 00
reg2e: 00
//Distance from end of broad pulse to negative-to-positive transition of tri-level sync (HDTV)
//Setting based on: 0x4805 0464(19:8) [0x3e]
reg2f: 3f
reg30: 00
// reg 0x31 - 0x33 for SDTV
reg31: 00
reg32: 58
reg33: 00
// reg 0x34 - 0x35: 0x63e
//Setting based on: 0x4805 0464(31:20) [0xfe], 0x4805 0464(19:8) [0x3e] and 0x4805 047C(10:0) [0x4ff]
// 0xfe + 0x3e + 0x4ff + 3 = 0x63e
reg34: 06
reg35: 3e
// 0x36-0x37: starting line number
reg36: 00
reg37: 01
//output format: ATSC mode 720P
reg38: 82
// 0x39 -0x3a: Generic mode frame size: 745 lines / frame in 720p mode: 0x2E9
//Setting based on: 0x4805 0468(15:8) [0x14], 0x4805 0468(27:20) [0x05] and 0x4805 047C(26:16) [0x2cf]
// 0x14 + 0x05 + 2cf + 1 = 0x2E9
reg39: 27
reg3a: e9
reg3b: ff
//Color bar pattern, not used
reg3c: 80
// 0x3d - 0x40: DAC in normal operation
reg3d: 00
reg3e: 00
reg3f: 00
reg40: 00
//0x41-0x4F: Clip/Scale/Multiplier Control, default values applied
reg41: 40
reg42: 40
reg43: 40
reg44: 53
reg45: 3f
reg46: 3f
reg47: 40
reg48: 40
reg49: 40
reg4a: 08
reg4b: 00
reg4c: 00
reg4d: 00
reg4e: 00
reg4f: 00
//0x50-0x70 breakpoint<n> line number and Line type for dtg2_bp<n>, all default
reg50: 00
reg51: 00
reg52: 00
reg53: 00
reg54: 00
reg55: 00
reg56: 00
reg57: 00
reg58: 00
reg59: 00
reg5a: 00
reg5b: 00
reg5c: 00
reg5d: 00
reg5e: 00
reg5f: 00
reg60: 00
reg61: 00
reg62: 00
reg63: 00
reg64: 00
reg65: 00
reg66: 00
reg67: 00
reg68: 00
reg69: 00
reg6a: 00
reg6b: 00
reg6c: 00
reg6d: 00
reg6e: 00
reg6f: 00
reg70: 60
//reg 0x71 -0x78, for VS__OUT and HS_OUT, not used
reg71: 00
reg72: 02
reg73: 03
reg74: 00
reg75: 03
reg76: 00
reg77: 07
reg78: ff
// reg 0x79 -0x7c: DTG horizontal/vertical delay: copied from the DM6446 sample code
reg79: 00
reg7a: 60
reg7b: 08
reg7c: 06
//reg 0x7d - 0x7e Pixel count readback
reg7d: 00
reg7e: 00
//reg 0x7f: Interlaced/progressive-scan indicator, 0 for progressive
reg7f: 00
//reg 0x80: Line count readback
reg80: 00
// not documented, default value
reg81: 00
// reg 0x82: output mode and SYNCs polarity: YPbPr mode, Positive polarity for VS_IN and HS_IN, Negative polarity for FID.
reg82: 1b
// Reg 0x83-0x85: CGMS Control, default
reg83: 00
reg84: 00
reg85: 00
//not documented
reg86: 00
reg87: 00
reg88: 00
reg89: 00
OMAP3 Display Controller Registers:
Reg: 0x4805 0400: 00000030
Reg: 0x4805 0410: 00002015
Reg: 0x4805 0414: 00000001
Reg: 0x4805 0418: 00000020
Reg: 0x4805 041c: 0000d640
Reg: 0x4805 0440: 00018309
Reg: 0x4805 0444: 00000204
Reg: 0x4805 0448: 000003ff
Reg: 0x4805 044c: 00000000
Reg: 0x4805 0450: 00000000
Reg: 0x4805 0454: 00000000
Reg: 0x4805 0458: 00000000
Reg: 0x4805 045c: 00000250
Reg: 0x4805 0460: 00000000
Reg: 0x4805 0464: 0fe03e30
Reg: 0x4805 0468: 01400503
Reg: 0x4805 046c: 00000000
Reg: 0x4805 0470: 00010002
Reg: 0x4805 0474: 000000ff
Reg: 0x4805 0478: 00000000
Reg: 0x4805 047c: 02cf04ff
Reg: 0x4805 0480: 8e000000
Reg: 0x4805 0484: 8e000000
Reg: 0x4805 0488: 00000000
Reg: 0x4805 048c: 02cf04ff
Reg: 0x4805 04a0: 00000091
Reg: 0x4805 04a4: 03fc03bc
Reg: 0x4805 04a8: 00000400
Reg: 0x4805 04ac: 00000001
Reg: 0x4805 04b0: 00000001
Reg: 0x4805 04b4: 00000000
Reg: 0x4805 04b8: 00000000
