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PCIe 6657 EVM connected to linux : Cannot Read/Write to Bar0 from Linux

claude.chausse
Intellectual 430 points

Hi, 

I am working on a project where I have to connect a ARM processor running Linux to an TI 6657 EVM.  My Arm/Linux is not from TI but the PCI interface have proven to be working fine since I can connect a Standard off-the-shelf PCIe wifi adapter and it works seamlessly.   

My 6657 is setup in PCIe Boot mode (so in EP mode) with a BAR configuration where BAR1 size is 4M. My Linux host only use the Bar0 and BAR1 since there is not enough reserved memory for the other ones.

When I boot my Linux with the 6657EVM connected I get a PCIe link up with the following BAR mapping

Region 0: Memory at 01500000 (32-bit, non-prefetchable) [size=4K]
Region 1: Memory at 01000000 (32-bit, prefetchable) [size=4M]

The problem is that whatever I do, I cannot reliably read the BAR0. I read something but it does not relate to the PCI register on the TI Side. What I read is always the same in the whole region. And the worst is that I don't read the same thing depending on the method I use (using ioread or direct memory access) .

Obviously, I cannot do anything if I cannot access the BAR0 because that is the way I will be able to configure translation for BAR1. 

does anybody have ideas on what  could be the problem ? To I have to fix it by playing with the PCI configuration  on the RC/Linux side ? If yes that change is required for it to work ?

Thank you

  • 0
    TI__Guru* 95265 points

    Claude,

    BAR0 is always pointing to PCIE MMR registers region (0x2180_0000). We did test of 6657 EVM with a standard Linux PC before, it worked. When you read EP's PCIE MMR via BAR0, how the value looks like? Do you have a stable PCIE link (the 6657's 0x2180_1728 last 5 bit should be 0x11)? If the link is not stable, then the read is invalid.

    Regards, Eric

      

  • 0 in reply to lding
    Intellectual 430 points

    Hi Eric, 

    I know that BAR0 is pointing to the PCIE register that is why I can say that it is wrong because I expected the PID on word 0 and I don't get it. But the problem with 6657 is not only not getting that I don't get the right data but the data I get is not consistent. 

    I did a test yesterday and I connected a 6678 EVM (instead of the 6657) and it worked right away without any change on the ARM/Linux side. I can read the PID (i.e. 0x4E301101) on word 0. So this proves that the PCI Hardware and software is good on my ARM/Linux box. 

    Also I noticed that there are a lot of differences between the  BAR configuration on the 6678 and on the 6657. 

    The first big difference it that the 6678 BAR0 size is 1M while the BAR0 on the 6657 is 4K. But the 6678 has also more bars configured.

    I am suprised that you have a standard linux working with the 6657 because in another thread, someone from TI told me that it was not possible to make the 6657 work with a X86 Linux because of a clock issue. With the clock issue, I could not even get a Link up. Not on the Arm , I get the Link up and lspci works but the data on BAR0 is wrong.

    Is it possible that in PCIe boot mode , the PCIe configuration is bad on the 6657 ? On is it a problem with the EVM ? 

    I would really appreciate that we get me some hints on how to proceed. 

    Thanks

     

  • 0 in reply to claude.chausse
    TI__Guru* 95265 points

    If 6678 EVM worked on your setup, I think there should be now issue at PCIE RC side. Can you tell the switch pin settings in your 6657 EVM?

    For the mentioned Linux PC worked with 6657 EVM, the used 6657 EVM is alaph or beta card, NOT PRODUCTION CARD. The alpha/beta still use IBL like we did for 6678 EVM, so it worked. Sorry for the confusion! The production 6657 EVM has IBL removed, and it directly boot from ROM.

    I will look for a production 6657 EVM and try it probably with another DSP card running Linux as PCIE RC. Do you happen to know if 6678EVM as RC (runing DSP PCIE code in no boot mode) and 6657 EVM as EP (PCIE boot mode), can 6678 read 6657's PCIE MMR correctly via BAR0? This info can give me some flexibitly how to set-up a test system.

    Regards, Eric    

  • 0 in reply to lding
    Intellectual 430 points

    Unfortunately, I don't have what it needs to connect a 6678 in RC mode to a 6657 in EP mode. I would really appreciate if that could be tested on your side. I would really help me. 

    I will concentrate on my setup which causes me enough problems. 

    My plan is to try find a recipe that works on the 6678 using  my own PCIe initialization code (not the EVM boot code) using CCS. Then if it works, I will try the same code on the 6657.

    Anyway, here is 2 pictures, First One is 6678 and secondone is for the 6657 .

  • 0 in reply to claude.chausse
    TI__Guru* 95265 points

    Thanks! "My plan is to try find a recipe that works on the 6678 using  my own PCIe initialization code (not the EVM boot code) using CCS. Then if it works, I will try the same code on the 6657."

    We already have PCIE boot code use CCS under C:\ti\pdk_C66xx_1_1_2_6\packages\ti\drv\exampleProjects\PCIE_exampleProject. It is CCS project, build and run (DSP in no-boot mode). Is this what you are looking for?

    Regards, Eric

  • 0 in reply to lding
    Intellectual 430 points

    Yes this is exactly what I had in mind. I will start with that code and see if I can make it work on the 6678 first then on the 6657.

  • 0 in reply to claude.chausse
    TI__Guru* 95265 points

    At least I knew C6678 is working, I used the PDK code mentioned last month to do a PCIE test between a PCIE RC (Linux) ---- PCIE EP (6678 EVM). I didn't try 6657EVM.

    Regards, Eric