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Camera ISP in OMAP3530

keshan
Prodigy 140 points


First thing am trying is to store the image data straightly in OMAP memory without frontend and backend processing. After got successful in this i will try for frontend and backend processing.

Please refer the section 12.4.1.1.2. In this section i am planing to use path C. Please let me know whether this is correct option to store directly in memory. 

From section 12.4.1.1.1,12.4.1.1.2,12.4.1.1.3 my understanding is all the images must pass through CCDC module in which the sub modules like optical clamping, faulty pixel correction,data formatter,reformatter,LSC can be enabled or disabled individually.Please clarify this.

For storing image data straightly in memory with out video processing, Please clarify the following

1. i must enable(Program) the Timing CTRL, CCDC,SBL,CBUFF modules in Camera ISP

2. Whether i need cam_hs, cam_vs,cam_fld from the camera which is going to interface with Camera ISP.

3.What is the purpose of CCDC_VD0_IRQ,CCDC_VD1_IRQ,CCDC_VD2_IRQ?What may the correspondig interrupt handler do?

4.ISP configuration details

Thanks and Regards,

kathir

  • Prodigy 10 points

    To add on to what Kathir has mentioned in his post,

    We are working on bringing out RAW data from a DINI-9200K FPGA based board with a Virtex-5 FPGA. The interface on the DINI board is a standard VDI interface that is it comprises of the following signals;

    1) cam_d [11:0]

    2) cam_hs

    3) cam_vs

    4) cam_pclk

    We are sending out 8-bit data @ 130 MHz from the DINI board through a custom patch board that we have designed in house and that is interfaced to a ZOOM kit (1010047C) from Logic PD Inc.

    So the data that is being sent out is in the order 8 bits of R, 8 bits of G, and 8 bits of B respectively. The problem that we are seeing at the OMAP side is that we are missing data (i.e. we are missing one complete byte intermittently) and the data that we see in the OMAP DDR is corrupted. Things seem to get better at lower frequencies say 30 MHz or so. However, at lower frequencies we notice that the cam_d[0] and cam_d[1] bits are corrupted.

    Our Custom card is Impedance matched as well as length matched. Where are we going wrong? Could some of you folks out there suggest a solution to this problem?

    Thanks,

    Kartik.

     

  • in reply to kartik subramanian
    Prodigy 60 points

    Hello Kartik,

    It seems we're experiencing the same problem.

    I'm sending 8bit @ 50MHz RAW data from FPGA in 8bit packed sync mode and sometimes cam_d[0] and cam_d[1] bits are corrupted.

    Did you resolve your problem?

    Regards,

    Igal