Facing issue in making external ram region cache-able in omapl138[DSP- TMS320C6748]

Hi Rishabh,

Thanks for your post.

As per your above post, you mentioned like, you are using C6748 DSP but you have used xdc.useModule as c64p family of DSP, so, I need a clarification on the below line:

Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');

But alternatively, you shall use the CSL command sequence to enable caching of external memory location as mentioned in Cacheablility topic (Section 2.3) in the C674x DSP cache user guide as below:

http://www.ti.com/lit/ug/sprug82a/sprug82a.pdf

In the above user guide, there is an example 2-2 C674x CSL command sequence to enable caching and in addition to this, you  shall go for optimizing cache performance by reduce the number of cache misses and the number of stall cycles per miss. Please find the details in Section 3.1.2 in the above Cache user guide.

Please also refer C674x DSP megamodule reference guide to get details on cache control registers as below:

http://www.ti.com/lit/ug/sprufk5a/sprufk5a.pdf

In general, it is expected like, external memories (SDRAM or DDR) should eventually have more delays due to any additional self refresh cycles and external setup/hold time considerations etc.

Thanks & regards,

Sivaraj K

Hi Sivaraj,

Thanks for the reply.

I have already gone through these configuration. But as I have mentioned that we are trying to make RAM portion cacheable for us.

Like in our case RAM starts address starts from 0xC000_0000 - 256MB, which is further divided it into Linux[ARM - 224] & sysbios[DSP - 32].

So for that we need to enable MAR192 area for DSP region.

So how do we have to proceed in that?

As of now I don't see anything other then cfg file in particular to enable cache

As per your above post, you mentioned like, you are using C6748 DSP but you have used xdc.useModule as c64p family of DSP, so, I need a clarification on the below line:

Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');

I have also gone through the CSL API reference guide.

Can you guide us in how to enable particular area of DSP using any CSL command with any example?

Regards

Rishabh Jain

Hi Rishabh,

Thanks for your update.

It seems, If you are using SYS/BIOS, there is a conflict in using CSL cache APIs that perform cache-related initialization. Page 6-2 of the Bios v6 User's Guide (SPRUEX3G) warns of direct consequences if CSL and SYS BIOS are used together for interrupt, timer or cache functions. However, I see that the SyS BIOS 6 CACHE module has its own API. Most SYS/BIOS cache configuration is performed via your .cfg file. 

You can use the ROV tool (ti.sysbios.family.c64p.Cache view) to check whether the MAR bits that correspond to the range of DDR that you want to cache are enabled.  Refer to the cdoc for the ti.sysbios.family.c64p.Cache module for more information about MAR registers and for code snippets.

The 'cdoc' documentation found in your installation something like: C:\Program Files\Texas Instruments\bios_6_31_04_27\docs\cdoc\ti\sysbios\family\c64p\Cache.html, which describes the API, So please see the documentation for more information. 

Please refer the below E2E threads for more details which is mentioned above:

http://e2e.ti.com/support/embedded/bios/f/355/t/101328.aspx

http://e2e.ti.com/support/embedded/bios/f/355/t/111081.aspx

If you need to configure the cache using DSP/BIOS, please refer the below wiki:

http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache

Also, there is an rCSL example synopsis "CACHE_dspLib_fft" initializes the cache using the rCSL macros to configure the MAR bits to enhance the performance of source code located in external memory. You shall download the QuickStartOMAPL1x_rCSL_2.0 package to see such example for better understanding. Please refer the below wiki to download the source package:

http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL#Downloads

Thanks & regards,

Sivaraj K

Hi Rishabh,

Please use the attached Dsp.cfg file to configure external memory cache property and shall be used as reference.

6874.Dsp.cfg

Please check the below code snippet in the attached config. file:

/*  configure external memory cache property
 *
 *  C000_0000 - C7FF_FFFF   800_0000  ( 128 MB) Cache.MAR192_223
 *  ----------------------------------------------------------------------------
 *  C000_0000 - C1FF_FFFF   200_0000  (  32 MB) --------    don't care
 *  C200_0000 - C202_FFFF     3_0000  ( 192 KB) SR_0, SR-1  no-cache      MAR194
 *  C203_0000 - C2FF_FFFF    FD_0000  ( ~15 MB) --------    no-cache      MAR194
 *  C300_0000 - C37F_FFFF    80_0000  (   8 MB) DSP_PROG    cache enable  MAR195
 *  C380_0000 - C3FF_FFFF    80_0000  (   8 MB) --------    cache enable  MAR195
 *  C400_0000 - C7FF_FFFF   400_0000  (  64 MB) --------    don't care
 */

Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
Cache.MAR192_223   = 0x00000008;  /* xxxx xxxx xxxx xxxx xxxx xxxx xxxx 10xx */

Thanks & regards,

Sivaraj K

Hi Sivaraj,

Thanks for the reply.

PFA.

This is my configuration file and please ask for any query.

Regards

Rishabh Jain

Hi Rishabh,

Thanks for sharing the configuration file.

Please let me know your update, if any progress made.

Thanks & regards,
Sivaraj K

Hi Sivaraj,

I have gone through the links you have mentioned. But even after making changes I am not getting any success.

I am not able to understand one thing, as I have mentioned in my first post that:

1) if I am enabling cache from configuration file and try to get the status in C code why it is different or else there is no effect of configuration file.

2) One more question was this, how to enable any particular segment area cacheable like this using CSL function Cache.MAR192_223   = 0x00000008;  /* xxxx xxxx xxxx xxxx xxxx xxxx xxxx 10xx */?

Regards

Rishabh Jain

Hi Sivaraj,

It's been long since I get any reply from TI.

Can you please rectify my problem as mentioned in our earlier posts. This thing is very critical for our project so please go through it and guide us with proper solution.

Regards

Rishabh Jain

Hi Rishabh,

In my config. file, it is used as below:

Cache.MAR192_223   = 0x00000008;  But in your config. file attached above in your post, it is as:

Cache.MAR192_223 = 0x00008000

Why did we use it differently?

You could also try using the ROV tool (ti.sysbios.family.c64p.Cache view) to check whether the MAR bits that correspond to the range of external memory address to cache are enabled. 

Kindly check the cdoc for the ti.sysbios.family.c64p.Cache module for more information about MAR registers and for code snippets. The 'cdoc' documentation can be found in your installation directory as below:

~\Texas Instruments\bios_6_31_04_27\docs\cdoc\ti\sysbios\family\c64p\Cache.html, describes the API,

Thanks & regards,

Sivaraj K

HI Sivaraj,

As I am using 256MB RAM.

And divided First section linux = 224MB and second DSP = 32MB.

Further DSP is divided into two sections of 16 MB, first 16 MB includes ipc, shard memory while second contains code/data section together, so to enable cache on the second section I did this way:

Cache.MAR192_223   = 0x00000008;  But in your config. file attached above in your post, it is as:

Cache.MAR192_223 = 0x00008000

Are you clear now?

Regards

Rishabh Jain