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Memory architecture on DSP C6678

Alexandre NGUYEN
Intellectual 260 points

Hi,

My question is really easy but I can't find the information in the documents.

My colleague told me that the MSMCSRAM has similar characteristics that L2 cache.

-> Is it true ? If yes, where can I find this information ? I thought it would be in data sheet but I didn't find it.

Thanks,

Alex

  • 0
    Guru 10750 points

    Hi Alex,

    It is the prefetch you can read about it at sprugw0b.pdf -TMS320C66x DSP CorePac User Guide section 7.5

    Thanks,

    HR

  • 0 in reply to HRi
    Intellectual 260 points

    Hi,

    Thank you for your answer. I was looking for some characteristics like the speed of accesses to both memories.

    In the section you told me, it's describing how the memory movements are made if I correctly understood.

    Is there a section in which the speed of accesses is written ?

    Thanks,

    Alex

  • 0 in reply to Alexandre NGUYEN
    Expert 2430 points

    Hi,

    The "Throughput Performance Guide" ( SPRABH2A1 ) provides a nice overview over the access latency and throughput of the various memory areas.

    Rule of thumb: While L2 access is somewhere arround 10-12 cycles on C6678, MSM access latency is usually higher 15-25 cycles.

    Not mentioned in those documents is the penality when accessing MSM from many cores simulatenously - which depends on your access patterns. When you are unlucky this results in a lot of banking conflicts.
    I recommend to put core-local data structures which are very frequently accessed into L2 when possible.

    Regards

  • 0 in reply to Clemens Eisserer
    Intellectual 260 points

    Hi,

    Thank you Clemens for your answer, that's exactly the type of document I was looking for ;)

    Regards,

    Alex