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How to move CSL wrote program with interrupt and EDMA serviced to DSP/BIOS environment

Other Parts Discussed in Thread: OMAP-L138, SYSBIOS

Hi,

I have a voice process program wrote in CCS with CSL support library in OMAP-L138 evm board, i can get it working good in CCS5, now i want to move it to Linux with DSPLINK, as the DSPLINK used DSP/BIOS, i need to move my program to DSP/BIOS environment, i have noticed the EDMA region, channel setting for to avoid infecting with Linux, but for the interrupt, i have not found some documents for how to move CSL wrote interrupt program to DSP/BIOS (i checked the DSPLINK used INT4/5, so i changed mine to INT6)

here is my INTC program in CCS with CSL 7608.dspintable.asm 

//Project  Name: quickStartOMAPL1x McASP Chip Support Library Example
//Texas Instruments Device Platform: Logic Product Development OMAP-L138 Experimentor Kit
//Copywrite (c) 2011 Texas Instruments Incroporated


/*===============================================================*/
/****************************LICENSE *****************************/
/*===============================================================*/
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*/
 
 
 
 /*===============================================================*/
/***************************INCLUDES *****************************/
/*===============================================================*/ 
#include "dspmm.h"
#include "mcasp.h"
#include "edma3.h"
#include "edma3_int_dispatcher.h"
#include <c6x.h>

Uint8 TxClockFail = 0x00;
Uint8 TxDMAFail = 0x00;
Uint8 TxFrameFail = 0x00;
Uint8 TxUnderFail = 0x00;



CSL_DspintcRegsOvly dspintcRegs = (CSL_DspintcRegsOvly) 	CSL_INTC_0_REGS;
//CSL_IdmaRegsOvly 	dspdmaRegs 	= (CSL_IdmaRegsOvly)   	CSL_IDMA_0_REGS;
//Uint32Ovly 			dsppdnRegs 	= (Uint32Ovly) 		DSPPDC_BASE_ADDRESS;
CSL_CacheRegsOvly 	dspcache 	= (CSL_CacheRegsOvly) 	CSL_CACHE_0_REGS;


void DSPMMInit(void){
	
	DSPPowerdownInit();					//Initialize DSP Power
	DSPInit();							//Initialize DSP Control Registers
	DSPCacheInit();						//Initialize DSP Cache Controllers
	DSPIntCtrlInit();					//Initialize DSP Interrupt Controller
}



void DSPPowerdownInit (void)
{
	//Leave C674x MegaModule Power Down alone since it defaults to enabled.
}


//Configure DSP Core
void DSPInit(void){
	
/* === Addressing Mode Register ===*/
	   CSL_FINST(AMR, CHIP_AMR_BK0, RESETVAL);
	   CSL_FINST(AMR, CHIP_AMR_BK1, RESETVAL);
	   CSL_FINST(AMR, CHIP_AMR_B7MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_B6MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_B5MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_B4MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A7MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A6MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A5MODE, LINEAR);
	   CSL_FINST(AMR, CHIP_AMR_A4MODE, LINEAR);

/* === Control Status Reigster === */
//CSR;
	
		CSL_FINST(CSR, CHIP_CSR_PWRD, RESETVAL);		//Keep C674 Powered Up
		CSL_FINST(CSR, CHIP_CSR_EN, LITTLE );			//Configure as Little Endian
		CSL_FINST(CSR, CHIP_CSR_GIE, DISABLE );			//Disable Global Interrupts
		
/* === Interrupt Clear Register === */
//ICR;
		ICR = 0xFFFF;		// clear any pending (old) interrupts

/* === Interrupt Enable Reigster === */
//IER;
		//Enable Non-Maskable (even maskable interrupts won't work unless this is on)
		CSL_FINST(IER, CHIP_IER_NMI, ENABLE );
	
		
		CSL_FINST(IER, CHIP_IER_IE04, DISABLE );				//Enable Interrupt 4 for McASP
		CSL_FINST(IER, CHIP_IER_IE05, DISABLE );			//Disable Interrupt 5
		CSL_FINST(IER, CHIP_IER_IE06, ENABLE );			//Disable Interrupt 6
		CSL_FINST(IER, CHIP_IER_IE07, DISABLE );			//Disable Interrupt 7
		CSL_FINST(IER, CHIP_IER_IE08, DISABLE );			//Disable Interrupt 8
		CSL_FINST(IER, CHIP_IER_IE09, DISABLE );			//Disable Interrupt 9
		CSL_FINST(IER, CHIP_IER_IE10, DISABLE );			//Disable Interrupt 10
		CSL_FINST(IER, CHIP_IER_IE11, DISABLE );			//Disable Interrupt 11
		CSL_FINST(IER, CHIP_IER_IE12, DISABLE );			//Disable Interrupt 12
		CSL_FINST(IER, CHIP_IER_IE13, DISABLE );			//Disable Interrupt 13
		CSL_FINST(IER, CHIP_IER_IE14, DISABLE );			//Disable Interrupt 14
		CSL_FINST(IER, CHIP_IER_IE15, DISABLE );			//Disable Interrupt 15

}


//Configure DSP Cache Controllers
void DSPCacheInit(void)
{

/* === Configure Level 1 Program Cache ===*/

/* === Configure Level 1 Data Cache ===*/

/* === Configure Level 2 Cache ===*/

}


//Configure DSP Interrupt Controller
void DSPIntCtrlInit (void)
{


	//Configure the Interrupt Controller for the following Map
	//  Reset -> Reset
	//  McASP -> CPUINT4
	//  All Others Unused

	/* ===Event Combiner ===*/
	//Event Combiner is not used because we simply don't need it.
	//However we should mask off all the events for good measure.
	
	dspintcRegs->EVTMASK[0] = (Uint32) (0xFFFFFFFFu);
	dspintcRegs->EVTMASK[1] = (Uint32) (0xFFFFFFFFu);
	dspintcRegs->EVTMASK[2] = (Uint32) (0xFFFFFFFFu);
	dspintcRegs->EVTMASK[3] = (Uint32) (0xFFFFFFFFu);
		/* ===Interrupt Selector ===*/

		//EDMA3 0 Channel Controller 0 Region Interrupt #1 will be send to CPU Interrupt # 4
		CSL_FINS(dspintcRegs->INTMUX1, DSPINTC_INTMUX1_INTSEL6, CSL_INTC_EVENTID_EDMA3_0_CC0_INT1);

		//MCASP Interrupt will be send to CPU Interrupt # 5 (highest priority of available interrupts
		//CSL_FINS(dspintcRegs->INTMUX1, DSPINTC_INTMUX1_INTSEL5, CSL_INTC_EVENTID_MCASP0INT);
		//edma3_int_hook(2, McASPInterruptHandler);

		/* Exception Handling */
		/* Turn this on to help catch software errors */
		TSR |= (1<<2);	// Set TSR.GEE

		/* ===Exception Combiner ===*/
		/* 	In general it is not recommended to use this capability.  Interrupting
		the CPU due to an exception can cause problems if it interrupts an
		uninterruptible loop. */

		/* ===Advanced Event Generator Mux ===*/
		//Leave as Default

		//Change the Interrupt Service Table Pointer from ROM to RAM address
		ISTP = (unsigned int) DSPintcVectorTable;
}



// Non-Maskable Interrupt Service Routine
// Either NMI pin was toggled or catastrophic software failure has occurred
interrupt void NMI_ISR(void){
	while(1);  //
	// 1.  Open a Register window and expand "Core Registers"
	// 2.  Look at EFR. If bit 1 is set (EFR=2) you have an internal exception.
	// 3.  For more detailed internal exception info see IERR.
	// 4.  NRP contains value of PC when the exception occurred.
	// 5.  If NRP doesn't give you a clue, you might also look at B3 which is
	//     used as the return address register in the C calling conventions
}

//Maskable Interrupt #4 Service Routine
interrupt void INT4_ISR(void){
}

//Maskable Interrupt #5 Service Routine
interrupt void INT5_ISR(void){
}

//Maskable Interrupt #6 Service Routine
interrupt void INT6_ISR(void){
	edma3_int_dispatcher(edma3_0cc0Regs);
}

//Maskable Interrupt #7 Service Routine
interrupt void INT7_ISR(void){
}

//Maskable Interrupt #8 Service Routine
interrupt void INT8_ISR(void){
}

//Maskable Interrupt #9 Service Routine
interrupt void INT9_ISR(void){
}

//Maskable Interrupt #10 Service Routine
interrupt void INT10_ISR(void){
}

//Maskable Interrupt #11 Service Routine
interrupt void INT11_ISR(void){
}

//Maskable Interrupt #12 Service Routine
interrupt void INT12_ISR(void){
}

//Maskable Interrupt #13 Service Routine
interrupt void INT13_ISR(void){
}

//Maskable Interrupt #14 Service Routine
interrupt void INT14_ISR(void){
}

//Maskable Interrupt #15 Service Routine
interrupt void INT15_ISR(void){
}















How i can change the INTC to adapt my program to DSP/BIOS environment?

Also, my program is cmd as following to put code to IRAM

-----------------

-stack 0x1000
-heap 0x1000

/* =========================================================================*
* Specify the System Memory Map *
* =========================================================================*/
MEMORY
{
L2: origin = 0x11800000 length = 0x00040000 /* Allocate L2 to Global Memory View*/
L1P: origin = 0x11E00000 length = 0x00008000
L1D: origin = 0x11F00000 length = 0x00008000
}

/* =========================================================================*
* Specify the Sections Allocation into Memory *
* =========================================================================*/
SECTIONS
{
.cinit > L2 /* Initialization Tables */
.pinit > L2 /* C++ Constructor Tables */
.const > L2 /* Constant Data */
.switch > L2 /* Jump Tables */
.text > L2 /* Executable Code */

.bss > L2 /* Global & Static Variables */
.far > L2 /* Far Global & Static Variables */
.stack > L2 /* Software System Stack */
.sysmem > L2 /* Dynamic Memory Allocation Area */

.cio > L2 /* C I/O Buffer */
.isr_vectors > L2 /* Interrupt Vectors */
}

-------------------------

But in the DSP/BIOS there is a BIOS codes loaded in IRAM and taken lot of space, can i put my codes to DDR?

Thank you