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IPC 3.x support for Jacinto 6 understanding

Mounesh Sutar
Prodigy 210 points

HI,

IPC3.x support is available to communicate between A15 cores and M4 Cores on Jacinto 6 boards. How these A15 and M4 processors are connected for data exchange ? Wish to understand through which port this IPC mechanism works ?

  • 0
    TI__Mastermind 29520 points

    Hello Mounesh,

    IPC 3.x connection does not use for data exchange. The IPUx subsystem (where is Cortex M4 cores) provides a multiprocessor communication interface for synchronizing tasks. Each Cortex-M4 core can interrupt the other Cortex-M4 core by setting up an interrupt register. Because the priority level for that interrupt can be defined, it is possible to choose the task level at which the interrupt will run.

    For more information about the communication features refer to section dedicated Interprocessor Communication
    (IPC) section in DRA7xx TRM.

    Other kind of IPC communication is managed through mailboxes. The mailbox function supports 2-way
    communication between a maximum of four users. This function relies on internal submodules, each
    supporting 1-way communication between one user referred to as the sender and another user referred to
    as the receiver.

    You can obtain more information about IPC ports as refer to section On-Chip Debug Support in DRA7xx TRM.

    For more information about Cortex-A15 MPCore, see the ARM Cortex-A15 MPCore Technical Reference
    Manual (available at infocenter.arm.com/help/index.jsp).

    Best regards,

    Yanko