McBSP and 192KHz/24bit codec

Typically with McBSP's, the maximum sample rate correlates to the maximum bit clock rate.  A quick glance at p. 201 of the datasheet (sprs505c.pdf) shows cycle times between 20-60 ns depending on the particular McBSP.  Remember that you also should look at setup times, hold times, etc.

Thanks Joe,

So it seems that OMAP3530 McBSP is more than adequate for the required 192KHz.

I'll utilize then an already written driver as a 'template' so do you think that Its better to base the new driver on the omap LTW4030 driver or on the omap AIC23 driver, both are there in linux, just not sure which fits better.

Is there any example that has TDM channel multiplexing in McBSP?

>>Is there any example that has TDM channel multiplexing in McBSP?

A nice thing about McBSP's is that they are about 90% the same on various TI processors.  So this app note is a litte older and might be overkill, but has a niceTDM example: http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=spra491a

Regarding which driver, I am not real familiar with OMAP35xx.  But either one that is close to the above app note and allows you to manipulate the McBSP registers should be ample.

Just one more thing.

Are there any hard-wired differences between the McBSP1/2/3/4/5 ports apart form the 5K buffer that the McBSP2 has in contrast to others that have 512Bytes?

There are recommendations for utilizatoin of specific applications on each McBSP port but does that reflect to an internal difference between the five ports? The question comes since the McBSP2 that has the large buffer is already allocated and I need to know if the remaining ports have any restriction in timings/data transfers/interrupt/dma etc.

In addition to the 5k buffer on McBSP2 there are also differences in pinout such that McBSP1 has a 6 pin configuration whereas 2,3,4, and 5 only have a 4 pin configuration, as well as the sidetone core which is only available on McBSP2 and 3. Apart from these primary differences the McBSP logic itself is largely the same between the various McBSP ports, so they can have the same basic configurations.

One difference to note is that the McBSPs are divided amongst both the CORE and PER power domains, with 1 and 5 on the CORE domain while 2, 3, and 4 are on the PER domain, so if you are going into low power modes where certain domains are off you may want to keep this in mind.

From a clocking perspective the McBSPs do have some different clock sources, this is probably best explained by section 21.3.2.2 of the TRM which discusses the clocking of each McBSP individually, for the most part they can all source from the mcbsp_clks pin or an internal PRCM generated clock.

Ok,

Now lets move to the driver required.

Since I have a beagleboard, I'll write a new ASoC driver based on a resident TWL4030 driver as a template.

The question is where should I declare that I'll use additionaly the McBSP1 (McBSP2 is used by TWL4030) for connection to my new codec device?

Is there a startup/setup somewhere whereas the board resident devices and interfaces are declared?

I knew from other architectures something like setup.c but apparently here we have something different and since I'm new to this I could use some help here too.

Thanks,

Christos