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The resolution range that omapl137'LCD support

Levone
Prodigy 180 points

Could some guy  figure out the resolution of omapl's LCD support? And the corresponding  frame rates. 

Also how to caculate the Frame rates? I suspect maybe it's depend on the PCLK and .... 

  • 0
    TI__Mastermind 37340 points

    By looking thru the data-sheet and user guides, you should be able to arrive that the max resolution supported in hardware is 1024x1024 and the max pixel clock is 150 MHz.  The resoluton, frame rate and pixel clock are related by the formula

        pixel clock = resolution (including blanking intervals)   x    frame rate

    Therefore, the resolution and pixel clock you choose to run at, will determine your frame rate limitation. 

    That said, from a software point of view, we support QVGA, WQVGA and CIF resolutions; you may need some driver mods to support other resolutions.

    For more details refer to the following thread: http://e2e.ti.com/forums/p/5041/18882.aspx#18882

    You may also find the following presentations on LCD driver for OMAP-L1 useful: http://tiexpressdsp.com/wiki/index.php?title=OMAPL1_PSP_WebEx_Presentations

  • 0 in reply to Juan Gonzales
    Prodigy 180 points

    I found the table as below, does that mean the  max pixel clock is  PCLK= F/2 =1000/23.81/2=21MH?  how could be 150MH...

     

    .

  • 0 in reply to Levone
    TI__Mastermind 37340 points

    Please note the (1) next to the F/2 in the table above.  This note states the F = frequency of LCD_PCLK

    According to the LCDC Users Guide (http://focus.ti.com/lit/ug/sprufm0a/sprufm0a.pdf), the pixel clock frequency is given by  LCD_PCLK = LCD_CLK /  CLKDIV.  CLKDIV ranges from 2-255  (actually from 0-255 but 0 and 1 are not valid for LCD_PCLK)

    The LCD_CLK is given by SYSCLK2.  Which is shown in the datasheet to be SYSCLK1/ 2 => (DSP/2) = 150MHz.   (http://focus.ti.com/lit/ds/symlink/omap-l137.pdf - page 67)

  • 0 in reply to Juan Gonzales
    Prodigy 180 points

    all right,I know what you mean ,that LCD_CLK<=150M, LCD_PCLK<=150/2=75M

    but why the min cycle time is 23,81ns ,for 1000/75=13.33ns.

    according to the timing table,pixel clock = F/2  and the note states F = LCD_PCLK ,so pixel clock =LCD_PCLK/2  <=75M/2=37.5MHz ,that would be a little close to 23.81ns.

    Any way,I am not sure the relationship between pixel clock and LCD_PCLK. in some place pixel clock = LCD_PCLK(pin description),but in that table pixel clock = LCD_PCLK/2(page 165 datasheet).

    On the onther hand ,user guider mentioned pixel clock = LCD_PCLK ranged (LCD_CLK/2 ,LCD_CLK/255).

    To Juan

                    Neither of the two bold formulas can achieve you mentioned max pixel clock  150MHz .Maybe I missed something..., Thanks!