I would like to do what is described in the following article:
http://tiexpressdsp.com/index.php?title=Linux_Aware_Debug
I would love to track down the author of the article as I cannot seem to get CCSV4Beta5 to work. I'm using a Blackhawk BH-USB-560M JTAG emulator with a BeagleBoard RevC2. I read that there was somthing wrong with the ES2 part, but since I'm using the ES3.1 part, this does not apply.
I am using the latest Linux Kernel in OE, namely V2.6.29. My u-boot and MLO are also from the latest OE. I have compiler debug symbols turned on, optimize for speed turned off and kernel optimization set at -O1.
When I launch the TI Debugger as described in the above article, I get an error message:
Trouble Reading Register:
Error 0x80002004/-1203
Fatal Error during: Register, Control,
The DAP access, address 0x000001E4, has returned a SLAVE error.
On the console I get the following:
<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>
OMAP 32K Watchdog Timer is disable
Putting DPLL into bypass before proceeding
Putting CORE DPLL into bypass before proceeding
Locking CORE DPLL
PRCM clock configuration IIA setup has been completed
SystemClock = 19.2 MHz
DPLL_MULT_VALUE = 242
DPLL_DIV_VALUE = 13
CORE_DPLL_CLK = 663.771 MHz
CORE_CLK = 331.8855 MHz
L3_CLK = 165.9427 MHz
MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks
common_sdram_init() completed
SDRC initilization for mDDR_Samsung_K4X51323PC completed
19.2MHz clock configuration IIa
CORTEXA8_CORE_VERSION = 0x411FC083
Cortex_A8_0: Trouble Reading Register: Error 0x80002004/-1203 Fatal Error during: Register, Control, The DAP access, address 0x000001E4, has returned a SLAVE error.
CORE_REVISION = 0x00100003
IS NOT COMPREHENDED BY THIS GEL FILE
Cortex_A8_0: GEL: Error while executing OnTargetConnect(): target failed to read memory at 0x20790600.
OMAP 32K Watchdog Timer is disable
Putting DPLL into bypass before proceeding
Putting CORE DPLL into bypass before proceeding
Locking CORE DPLL
PRCM clock configuration IIA setup has been completed
SystemClock = 19.2 MHz
DPLL_MULT_VALUE = 242
DPLL_DIV_VALUE = 13
CORE_DPLL_CLK = 663.771 MHz
CORE_CLK = 331.8855 MHz
L3_CLK = 165.9427 MHz
System Reset has occured.
Cortex_A8_0: Failed Software Reset
OMAP 32K Watchdog Timer is disable
Putting DPLL into bypass before proceeding
Putting CORE DPLL into bypass before proceeding
Locking CORE DPLL
PRCM clock configuration IIA setup has been completed
SystemClock = 19.2 MHz
DPLL_MULT_VALUE = 242
DPLL_DIV_VALUE = 13
CORE_DPLL_CLK = 663.771 MHz
CORE_CLK = 331.8855 MHz
L3_CLK = 165.9427 MHz
CPU Reset callback function has fired
<<<<<<<<<<<<<<>>>>>>>>>>>>>>>
Anyone know how to make this work?