In dm8148,How to set HSYNC style line capture & ACTVID style line capture ,hardware&software

jeffery wang

dear ti expert:

I used dm8148 to capture the 16bit yuv422 data from FPGA in Discrete Sync mode. And the VIP(VIP0,portA) didn't get the right data.

(1)In the HSYNC style line capture :the VIN[0]A_CLK / VIN[0]A_HSYNC /VIN[0]A_VSYNC are connected between DM8148 and fpga and the VIN[0]A_DE pin hang.

The FPGA used the uxga (1600*1200)to test DM8148 vip function,the info of video are belows:

pclk=50MHZ,hsclk=23KHZ,vsclk=18.5HZ Active Pixels:(1600*1200) total Pixels (2160*1250)

I set the vip mode to Discrete Sync mode and other parameters(VIP and ports,vpdma ),after start the vip ,

i get the hight and width of captured video from the VPDMA Outbound data Descriptors(Descriptor Write adds),

are 864*1250.（obviously,the width of captured video is wrong）

here the register value i dump form the 8148 device:

# ./memdev -d 0x48105500 0x50
48105500: 00000001 00402914 00000000 00000000    |.....)@.........|
48105510: 00000000 003ffe4f 00000000 00000000    |....O.?.........|
48105520: ffffffff         fffffffc       ffffffff f               fffffff    |................|
48105530: 036004e2 00000000 00000000 00000000    |..`.............|
48105540: 00000000 00000000 00000000 00000000    |................|
48105550: 00000000 00000000 00000000 00000000    |................|
48105560: 00000000 00000000 00000000 00000000    |................|
48105570: 00000000 00000000 00000000 00000000    |................|
48105580: 00000000 00000000 00000000 00000000    |................|
    (2)In the ACTVID style line capture :the VIN[0]A_CLK / VIN[0]A_DE/VIN[0]A_VSYNC are connected between DM8148 and fpga and the VIN[0]A_HSYNC PIN is alway LOW.

The test condition like (1)HSYNC style ,i also set the vip register to ACTVID style mode.But The the Outbound data Descriptors Write ,return the wrong width also.

./memdev -d 0x48105500 0x50
48105500: 00000001 0040a114 00000000 00000000    |.....)@.........|
48105510: 00000000 003ffe4f 00000000 00000000    |....O.?.........|
48105520: ffffffff ffffffff ffffffff ffffffff    |................|
48105530: 032004b0 00000000 00000000 00000000    |................|
48105540: 00000000 00000000 00000000 00000000    |................|
48105550: 00000000 00000000 00000000 00000000    |................|
48105560: 00000000 00000000 00000000 00000000    |................|
48105570: 00000000 00000000 00000000 00000000    |................|
48105580: 00000000 00000000 00000000 00000000    |................|
48105590: 00000000 00000000 00000000 00000000    |................|

.any help will be very appreciated!

over 12 years ago

0 jeffery wang over 12 years ago

Prodigy 230 points

multiple

0 Steve Clynes over 12 years ago in reply to jeffery wang

TI__Mastermind 43875 points

I don't believe that DE only mode is supported.

The main supported modes are embedded syncs and H/V/DE mode (all three signals)

H/V only might be supported but I don't know the details of this mode.

BR,

Steve

0 jeffery wang over 12 years ago in reply to Steve Clynes

Prodigy 230 points

hi steve:

thank for youe reply.

In hdvpss_01_00_01_37/vps_cfgVipParser.h,we can see this define:

typedef enum
{
VPS_VIP_LINE_CAPTURE_STYLE_HSYNC = 0,
/**< Use HSYNC style linecapture */

VPS_VIP_LINE_CAPTURE_STYLE_ACTVID,
/**< Use ACTVID style line capture */

VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE = -1
/**< Value is dont care */

} Vps_VipLineCaptureStyle;

In hdvpss_01_00_01_37/vps_capture.h,we can also see this enum :

typedef enum
{
    VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC = 0,
    /**< Single Channel non multiplexed mode */
    VPS_CAPT_VIDEO_CAPTURE_MODE_MULTI_CH_LINE_MUX_EMBEDDED_SYNC,
    /**< Multi-channel line-multiplexed mode */
    VPS_CAPT_VIDEO_CAPTURE_MODE_MULTI_CH_PIXEL_MUX_EMBEDDED_SYNC,
    /**< Multi-channel pixel muxed */
    VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VBLK,
    /**< Single Channel non multiplexed discrete sync mode with HSYNC and
        VBLK as control signals. */
    VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC,
    /**< Single Channel non multiplexed discrete sync mode with HSYNC and
        VSYNC as control signals. */
    VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VBLK,
    /**< Single Channel non multiplexed discrete sync mode with ACTVID and
        VBLK as control signals. */
    VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_ACTVID_VSYNC,
    /**< Single Channel non multiplexed discrete sync mode with ACTVID and
        VBLK as control signals. */
    VPS_CAPT_VIDEO_CAPTURE_MODE_MULTI_CH_LINE_MUX_SPLIT_LINE_EMBEDDED_SYNC,
    /**< Multi-channel line-multiplexed mode - split line mode */
    VPS_CAPT_VIDEO_CAPTURE_MODE_MAX
    /**< Maximum modes */
} Vps_CaptVideoCaptureMode;

And int the hdvpss_01_00_01_37vpsdrv_captureVip.c, we can see this mode of setting the vip

Int32 Vps_captVipParserConfigSetup ( Vps_CaptObj * pObj,
                                     VpsHal_VipConfig * vipInstConfig,
                                     VpsHal_VipPortConfig * vipPortConfig )
{
    Int32 status = FVID2_SOK;
    Vps_VipConfig *pUserInstConfig;
    Vps_VipPortConfig *pUserPortConfig;

    /*
     * setup VIP parser parameters
     */
    vipInstConfig->vipConfig.clipActive = FALSE;
    vipInstConfig->vipConfig.clipBlank = FALSE;

    vipPortConfig->ancChSel8b = VPS_VIP_ANC_CH_SEL_8B_LUMA_SIDE;
    vipPortConfig->pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING;
    vipPortConfig->disConfig.fidSkewPostCnt = 0;
    vipPortConfig->disConfig.fidSkewPreCnt = 0;
    vipPortConfig->disConfig.lineCaptureStyle =
        VPS_VIP_LINE_CAPTURE_STYLE_ACTVID;
    if ((pObj->createArgs.videoCaptureMode ==
        VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VBLK) ||
        (pObj->createArgs.videoCaptureMode ==
        VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC))
    {
        vipPortConfig->disConfig.lineCaptureStyle =
            VPS_VIP_LINE_CAPTURE_STYLE_HSYNC;
    }
    vipPortConfig->disConfig.fidDetectMode = VPS_VIP_FID_DETECT_MODE_PIN;
    vipPortConfig->disConfig.actvidPol = VPS_VIP_POLARITY_HIGH;
    vipPortConfig->disConfig.vsyncPol = VPS_VIP_POLARITY_LOW;
    vipPortConfig->disConfig.hsyncPol = VPS_VIP_POLARITY_LOW;

0 jeffery wang over 11 years ago in reply to jeffery wang

Prodigy 230 points

can anyone konws this question?

0 Louis Lu93481 over 11 years ago in reply to jeffery wang

TI__Expert 6025 points

Hi Jeffery,

Some observations from my side:

1. According to the VIP_PARSER_port_a register dump: 0x0040a114, is shown taking the FID from Pin, but I could not find the HW connection in their descriptions. I suspect the input is 800x600@60 progressive, so the FID should always ‘0’, and based on the register value, the value is from the PIN.

2. DISCRETE_BASIC_MODE is 1, that is Basic Discrete Mode, USE_ACTIVE_HSYNC_N is 1, which shown using the DE style line capture. Basicly, lines starting after an active transition on vsync will delineate a start of frame, lines are denoted by an inactive to active transition of actvid. From the test results they mentioned (50M clk or 27Mclk), the first point 0 was missed, so that means the VIP captured from the wrong starting.

So, my suggestions are:

1. Check the FID pin connections, if it connect to the FPGA, make sure the FPGA output in FID pin is low, otherwise it is required to pull down. The VIN[0]A_FLD is internal pull-up active.

2. For ACTIVID HSYNC mode, the configuration looked fine, and they can check the waveform of clk, actvid, vsync, and Y/UV signals output, especially to check if the line starting from point 0.

3. Try to change the polarity of ACTIVID.

Regards,

Louis

0 jeffery wang over 11 years ago in reply to Louis Lu93481

Prodigy 230 points

Hi Louis:

thank you for your kindly reply!

We had solved this issue,a low mistake,we didn't initialize the dss clk. I hated my negligence.

0 karthik reddy2 over 10 years ago

Intellectual 460 points

memdev to see register dump ,where can be get this exectable.

please kindly suggest

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In dm8148,How to set HSYNC style line capture & ACTVID style line capture ,hardware&software