USB performance when using SSC (spread spectrum clock) AM335X

Due to several constraints, the SSC performance of AM335x was not characterized as part of device validation. Most notable among these constraints are the pin-muxing requirements inherent in a complex SoC.

I am unaware of anyone using the SSC output functionality on this device.

We have enabled SSC and can confirm that it is working.

Do you know the jitter requirements for the USB phy refclk? In that way I should be able to figure out if my SSC setting is acceptable.

Since the SSC output of the PLL was not characterized, neither was the input tolerances of the USB PHY itself so I'm afraid we don't have that data available.

At this point the best option would be to run the actual USB2 compliance tests on your solution...there are electrical tests that will quantify your output jitter and indicate compliance issues. The tests and the related documentation can be found at USB.org.

Assuming your solution does pass the requisite USB tests, it's important to understand that since the SSC functionality was not characterized, its behavior cannot be guaranteed over process/voltage/ temperature ranges; this could cause problems down the line in a production environment. While it is possible for you to characterize the voltage and temp ranges on your platform, it is not possible to do the same with process. In other words, the part you test tomorrow may not exhibit the same SSC behavior as a part you test today.

Hi Folks,

The following customer problem seems to be related to the discusion above.

They have been looking into an issue with the AM3505 High Speed USB channel data download to a USB stick. They are finding high errors for larger size data transfers when we enable the L5 CLK spread spectrum feature. They are using the AM3505 to generate a 60MHz reference clock to drive the USB PHY reference clock. The USB PHY is  a USB3320 from SMSC. If they turn off the spread spectrum, there are no data errors. The USB PHY datasheet says it tolerates high levels of jitter on the 60MHz REFCLK input, so the effect of the spread spectrum on the 60MHz itself can’t be the issue.

Are there any known issues on the AM3505 High Speed USB interface when the L5 CLK spread spectrum is enabled?

What are the options if there is an issue with HS USB and L5 CLK when SSC is enabled?

Thanks.

Carlo,

When a PHY manufacturer talks about "high jitter tolerance", typically they are referring to the cycle-to-cycle jitter of the input clock, but in this case where SSC is enabled, it's actually the n-cycle jitter of the input clock that becomes the problem. Because USB devices recover the interface clock from the data stream itself, the introduction of SSC provides what is effectively a very large moving target for device clock recovery which will manifest as errors in larger transfers that may not be seen in smaller transfers. The USB2 specification was not written with SSC in mind and our recommendation is that it not be enabled in PLL's that source USB functions, either Peripheral or Host.

Hi, Per
  Could you tell me how to enable SSC, where is code , Thank you very much!