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DSPLink shared memory errors when remapping Linux and DSP

Other Parts Discussed in Thread: DM3730, OMAP3530

I have followed the instructions for changing the memory mapping of Linux and the DSP found at http://processors.wiki.ti.com/index.php/Changing_DSPLink_Memory_Map

My ARM side app and DSP app are running fine except that the I can no longer get my buffers transferred back and forth using DSPLink (specifically ring_io). This was working fine before I changed the memory addresses. Interestingly, I can still print DSP app debug traces on the ARM side app, so I believe I at least have the addressing setup correctly for the ARM and DSP applications.

I have changed the allocation to be 256M for ARM and 256M for DSP on my Gumstix Overo IronStorm (DM3730).

Here is an excerpt from dsplink-omap3530-base.tci

prog.module("GBL").C64PLUSMAR128to159  = 0x1FFF0000 ;/* Make sure DSPLINKMEM segment is NOT cached */

/*  ============================================================================

*  MEM : RESET_VECTOR

*  ============================================================================

*/

var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR");

RESET_VECTOR.base        = 0x90000000 ;

RESET_VECTOR.len         = 0x00000080;

RESET_VECTOR.space       = "code/data";

RESET_VECTOR.createHeap  = false;

RESET_VECTOR.comment     = "RESET_VECTOR";

/*  ============================================================================

*  MEM : Adjust DDR2

*  ============================================================================

*/

var DDR2 = prog.module("MEM").instance("DDR2");

DDR2.base             = RESET_VECTOR.base + RESET_VECTOR.len ;

DDR2.len              = 0x8FFFF80;

DDR2.space            = "code/data";

DDR2.createHeap       = true;

DDR2.heapSize         = 0x8000000;

DDR2.comment          = "DDR2";

/*  ============================================================================

*  MEM : DSPLINKMEM

*  ============================================================================

*/

var DSPLINKMEM = prog.module("MEM").create("DSPLINKMEM");

DSPLINKMEM.base             = DDR2.base + DDR2.len ;

DSPLINKMEM.len              = 0x00030000;

DSPLINKMEM.createHeap       = false;

DSPLINKMEM.comment          = "DSPLINKMEM";

/*  ============================================================================

*  MEM : DSPLINKMEM

*  ============================================================================

*/

var POOLMEM = prog.module("MEM").create("POOLMEM");

POOLMEM.base             = DSPLINKMEM.base + DSPLINKMEM.len ;

POOLMEM.len              = 0xD0000;

POOLMEM.createHeap       = false;

POOLMEM.comment          = "POOLMEM";

Here is an excerpt from CFG_OMAP3530_SHMEM.c

#define  RSTENTRYID         0u

#define  RESETCTRLADDR      0x90000000u

#define  RESETCTRLSIZE      0x80u

 

#define  CODEENTRYID        1u

#define  CODEMEMORYADDR     (RESETCTRLADDR + RESETCTRLSIZE)

#define  CODEMEMORYSIZE     0x8FFFF80u

 

#define  SHAREDENTRYID0     2u

#define  SHAREDMEMORYADDR0  (CODEMEMORYADDR + CODEMEMORYSIZE)

#define  SHAREDMEMORYSIZE0  0x5000u

 

#define  SHAREDENTRYID1     3u

#define  SHAREDMEMORYADDR1  (SHAREDMEMORYADDR0 + SHAREDMEMORYSIZE0)

#define  SHAREDMEMORYSIZE1  0x2B000u

 

#define  POOLENTRYID        4u

#define  POOLMEMORYADDR     (SHAREDMEMORYADDR1 + SHAREDMEMORYSIZE1)

#define  POOLMEMORYSIZE     0x000D0000u

  • Hi Bryce,

    Are you able to run the DspLink RingIO sample with your memory map changes?  If not, you could try backing out the memory map changes, then adding in the changes one at a time, until it no longer works.  Usually when there is a memory map conflict between the Arm and the DSP, PROC_start() will fail.  What kind of failure behavior are you seeing?

    Also, what version of DSPLink are you using?  You could attach the CFG.c and .tci files so that I can diff them with what's in the product.

    Best regards,

        Janet

  • Thanks for the response. I found the issue. The root of my problem was caching. Prior to my remap, the DSPLink shared memory was outside of the cachable region specified in the .tci file.

    prog.module("GBL").C64PLUSMAR128to159  = 0x00000080 ;

    When I changed everything in the DSP space to be cacheable (0xFFFF0000), my data going back to the ARM side was not correct since the DSP wasn't Invalidating the cache before releasing the buffer.

    If I use the write buffer instead of the same read buffer to write stuff back or if I do a HAL_cacheWbInv on the read buffer, it works fine.

    Bryce