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Sitara AM3352 Ethernet with TLK105 Phy, working in u-boot but not in Linux

Torben Frenzel
Prodigy 180 points
Other Parts Discussed in Thread: TLK105, AM3352

Hi,

I have a custom board with an AM3352 processor and two TLK105 ethernet phys.

Both phys are connected via RMII, and we have established (via boundary scan) that they both seem to be working.

In u-boot, I was able to ping another machine via eth0 after modifying the pinmux matrix and configuring RMII. I understand that u-boot supports only one network device, which is why I have not tried to use eth1 here.

In Linux, I was able to get both ethernet ports listed as interfaces (eth0, eth1). MDIO communication with the phys seems to be ok, their ID is read during boot and I get a message on the console when I plug / unplug a cable into / from eth0 (not eth1 though). I used some code from the Sitara Linux Board Porting exercise to get this far.

However, I am unable to send or receive anything over the network and the ethernet port constantly changes it's status (up/down).

I am pretty sure that there is some problem with either my pinmux in Linux or that the cpsw is not configured for RMII. I deleted every pinmux entry from the board file I could find, because I prefer doing all the muxing in u-boot. It's much easier to find errors if you don't need to look in dozens of places...

Could someone please point me to the kernel source files I need to edit to

1. make sure no pinmuxing (at least, no wrong pinmuxing...) takes place and

2. configure the cpsw correctly for two TLK105 ethernet phys connected via RMII

Thanks

Tom

  • 0
    TI__Mastermind 25235 points

    Hi,

    Torben Frenzel said:
    1. make sure no pinmuxing (at least, no wrong pinmuxing...) takes place and

    The pinmuxing in the kernel from TI's SDK happens inside <kernel_dir>/arch/arm/mach-omap2/board-am335xevm.c

    Torben Frenzel said:
    2. configure the cpsw correctly for two TLK105 ethernet phys connected via RMII

    Have you read the AM335x CPSW Driver's Guide: http://processors.wiki.ti.com/index.php/AM335x_CPSW_%28Ethernet%29_Driver%27s_Guide

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Prodigy 180 points

    Miroslav,

    thank you for your response.

    I got rid of every pinmux entry in the board file (I copied it and started a new board file for our custom board at the beginning of development), so it seems that pinmuxing is not the issue.

    I read the CPSW driver guide, but unfortunately there is not much information there. The kernel is correctly configured for Dual Standalone EMAC. It still seems to me that the CPSW is somehow using the wrong interface (RGMII perhaps, or MII), or that some configuration step is missing. I added the "am33xx_cpsw_init_generic" function from http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Linux_Board_Port to "mach-omap2/devices.c", but since this was written to work on the EVM-SK which uses different MIIs I'm not sure that the CPSW is configured correctly.

    Could you please summarize how the CPSW configuration process works in the Linux kernel?

    Thanks

    Tom

  • 0 in reply to Torben Frenzel
    TI__Genius 15510 points

    Are you using the file system from the SDK? If so, there is a utility called devmem2 that will dump register information. Can you type in

    devmem2 0x44e10650

    And reply with the result.

    Steve K.

  • 0 in reply to Steve Kipisz
    TI__Genius 15510 points

    I'm guessing that in board-am335xevm.c you modified

    am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);

    to be AM33XX_CPSW_MODE_RMII. If you look in devices.c you will see this code

             case AM33XX_CPSW_MODE_RMII:
                     gmii_sel = AM33XX_RMII_MODE_EN;
                     break;

    And in control.h you'll see

    :#define AM33XX_RMII_MODE_EN           ((1 << 0) | (1 << 2))

    So the upper bits that specifiy clock input mode are not getting set. That's my theory.

    Steve K.

  • 0 in reply to Steve Kipisz
    Prodigy 180 points

    Steve,

    I'm currently not using the SDK filesystem, but I could prepare an SD Card so I can use devmem2.

    I did however add the necessary bits to the gmii_sel register (we are sourcing the 50MHz clock from an external oscillator) , and now the link is stable. I'm still not able to send or receive anything though...

    Tom

  • 0
    Prodigy 10 points

    Tom,

    I too have a custom board using the TLK105 PHY. I'm trying to add support to my board's u-boot for this chip. I see that you have successfully done this. Could you possibly share your u-boot source for others to do the same?

    Thank you very much in advance.

    /Charlie