• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 100 subscribers
  • Views 1482 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x MMU Level 2 Page Table

Patrick Ruf
Genius 5095 points

Hi,

StarterWare has a first level page table MMU implementation. Are there any plans to expand this to a second level page table implementation?
If no, does TI have any examples on how to implement a second level page table?

I have to translate a non-contiguous physical memory space (NOR flash with pin-muxing limitations) into a virtually contiguous memory. Contiguous block size on physical memory is 512kB. Total memory size is 2MB.

The idea is to have the two 1MB sections translated with two second level page tables.

Thanks and best regards,

Patrick

  • 0
    TI__Genius 17370 points

    Hi Patrick,

               From StarterWare there are no plans to expand to second level page table, in order to keep the example applications simpler. I am not aware of any other no-OS code configuring 2nd level page table.

              Is it possible to refer linux for this configuration ?

    Regards

    baskaran

  • 0 in reply to Baskaran Chidambaram
    Genius 5095 points

    Hi Baskaran,

    Linux is not an option as we have some realtime requirements. I just studied some ARM manuals and programming guides concerning this MMU topic and I think I will try an implementation.
    But I have one more question: In the StarterWare implementation there is also the page type "Supersection". Is this fully implemented? Any permormance benefit in using Super Sections?

    Thanks and best regards,
    Patrick

  • 0 in reply to Patrick Ruf
    TI__Expert 5960 points

    Hi Patrick,

    I would recommend the "Cortex -A Series Programmer's Guide" from ARM.  I see it is up to Version: 3.0.

    It covers MMU translation table setup very well.  It covers why you may want to use Super Sections.

    See section 8.6 Choice of page sizes.  

    Also with regards, to Linux, I think Baskaran was saying you could take a look at the Linux MMU code because it does use level 2 page tables.

  • 0 in reply to Jeff L
    Genius 5095 points

    Hi Jeff,

    Thanks for your recommendations. That's exactly what I have done today. I now have an implementation that does what it has to do so far. I will now try to tweak it into Supersections and Large Page.

    Thanks to all the contributors

    Best regards,
    Patrick

  • 0 in reply to Patrick Ruf
    TI__Expert 6580 points

    There is a preliminary work-in-progress code, that is available in the c file inserted below, along with a simple test code. Hope this helps. It would also be helpful for us to know, how you plan to use the pages thus allocated,

    6874.mmu_2level_arm.c

    8623.2level_testcode.c

    regards

    Prabindh