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C6678 SRIO 4x ‘port width’

Luke Williams
Prodigy 110 points

I am working with a C6678 DSP-FPGA SRIO connection configured for 1-4x port.

The RIO_PLM_SP(n)_PATH_CTL and SP(n)_CTL (n) settings of my configuration are as below.

RIO_PLM_SP(0)_PATH_CTL        0x00000404 (Hex)           

RIO_PLM_SP(1)_PATH_CTL        0x00000404 (Hex)           

RIO_PLM_SP(2)_PATH_CTL        0x00000404 (Hex)           

RIO_PLM_SP(3)_PATH_CTL        0x00000404 (Hex)     

RIO_SP(0)_CTL 0xD0600001 (Hex)                           

RIO_SP(1)_CTL  0x00600001 (Hex)                           

RIO_SP(2)_CTL  0x00600001 (Hex)                           

RIO_SP(3)_CTL  0x00600001 (Hex)           

 

The Port Width field in RIO_SP(0)_CTL which is ‘read only’ shows as 0b11 indicating support for 2x besides 4x.

What settings would be required to change this field to 0b01 indicating support for 4x and not for 2x? The reason I ask this question is that I use a gel script to verify my SRIO configuration settings and I get the following error when running the ‘SRIO Errors Scan (Physical)’ GEL function from the script.

C66xx_0: GEL Output:  Problem(PORT_WIDTH): Port0 widht  **DOES NOT MATCH**  with PLM path configurations

C66xx_0: GEL Output:  Reason & Solution: Check PLM path configuartion settings. The current PLM path settings might not be legal

I obtained the script  6406.TCI6678_8_Srio_v0.13.gel from an earlier forum posting. http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/248398/870321.aspx

Thanks.

Luke

  • 0
    TI__Genius 13215 points

    Hi Luke,

    It looks like there is an error in how the gel file interprets the contents of the SRIO registers.

    For a 1 4x port configuration, the 4 lanes are mapped to port 0. Looking at the RIO_PLM_SP(0)_PATH_CTL register contents, it is set for configuration 4 and mode 4. Path mode 4 (1 4x port) is valid for path configuration 4.

    SRIO modes by configuration:

    These values control the port width field, bits 31 and 30 of the RIO_SP(0)_CTL register, which indicate that 2x mode and 4x mode are supported (both bits are 1's).

    All of these setting are correct and not in conflict with each other. The gel file should not report this as an error. Are you having issues communicating between your devices? If so, some of the follow information would be helpful to better assist you.

    1. Are you using an example included in TI's MCSDK?
      1. If so, which example?
      2. Have you modified the example at all?
      3. Which version of the MCSDK are you using?
    2. How are you testing your setup?
    3. How do you know that an error has occurred?

    Thanks,

    Clinton

  • 0 in reply to Clinton Rodgers
    Prodigy 110 points

    Hi Clinton,

    Thank you for your explanation.  I suspected that the gel file should not report an error and was looking for a confirmation. Otherwise, I do not have issues communicating between the devices.  But, it would be great if you could pass on a working gel file if you have access to one.

    Thanks.

    Luke