Other Parts Discussed in Thread: OMAP3530
Hello,
Could anyone share a sample Configuration Header (CH) setting including MMCHS_SYSCTL that achieves the maximum clock speed (48MHz) on OMAP3530 or figure out what's wrong with my setting below?
For faster boot, I have successfully removed X-Loader, porting its clock settings (PLL,SDRAM,MMC,etc) to u-boot.
My u-boot now works as MLO with Configuration Header, which contains the clock initialization part previously included in X-Loader.
However, although I can set CHSETTINGS and CHRAM without a problem, only mmchs_sysctrl in the CHMMCSD part does not match the value with the one I set. It seems the OMAP ROM Code automatically re-set the clock rate to something much slower than 48MHz. For example,
Set value in CH vs Observed value in u-boot (before initializing mmc)
ex.1 0x000E0087 -> 0x000E0387
(0x000E0087 corresponds to 96/2=48MHz, 0x000E0387 does to 96/14 = 6.857...which looks weird)
ex.2 0xFFFFFFFF -> 0x000E0207
(0xFFFFFFFF : does not update the register. 0x000E0207 : 96/8 = 12MHz. This looks weird too since OMAP3530 TRM says the default value is "19.2-MHz clock during data transfer mode" in 25.4.8.2.4 CHMMCSD. Why 12MHz appears here?)
ex.3 0x000E0207 -> 0x000E0387
(E0207 should be an acceptable value from the experiment above but why this falls back to E0387???)
ex.4 0x00000000 -> 0x000E0007
(0x000E0007 : The clock is bypassed. Somehow this achieved the fastest boot time)
The code used to generate CH is below:
/* CHMMCSD section in x-loader/scripts/signGP.c */
{
0xc0c0c0c4,
0x01, //0x00:ignore this section. Others:enable this section.
{0x00, 0x00, 0x00},
0x000E, // __u16 mmchs_sysctrl_msb; //register value. 0x4809C12C
0x0087, // __u16 mmchs_sysctrl_lsb; //0x0087:should run at 48MHz.
0x00000002, //__u32 bus_width. 1=1bit, 2=4bits, 4=8bits
},
Any comment would be highly appreciated.
Thank you,
Nobu
