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ARM 335x unspecified registers

Sinthu Raja
Prodigy 60 points
Other Parts Discussed in Thread: AM3358

Following are the registers which are not in the TRM  provided by the TI, where can i refer and guide me whether to use these registers or not.

DDR_PHY_BASE_ADDR 0x44E12000
Not available Registers in TRM
Base Addr Offset
CMD0_CTRL_SLAVE_FORCE_0 0x44E12000 0x020
CMD0_CTRL_SLAVE_DELAY_0 0x44E12000 0x024
0x44E12000
CMD1_CTRL_SLAVE_FORCE_0 0x44E12000 0x054
CMD1_CTRL_SLAVE_DELAY_0 0x44E12000 0x058
0x44E12000
CMD2_CTRL_SLAVE_FORCE_0 0x44E12000 0x088
CMD2_CTRL_SLAVE_DELAY_0 0x44E12000 0x08C
0x44E12000
DATA0_RD_DQS_SLAVE_RATIO_1 0x44E12000 0x0CC
DATA0_WR_DQS_SLAVE_RATIO_1 0x44E12000 0x0E0
0x44E12000
DATA0_WRLVL_INIT_RATIO_1 0x44E12000 0x0F4
DATA0_GATELVL_INIT_RATIO_1 0x44E12000 0x100
DATA0_FIFO_WE_SLAVE_RATIO_1 0x44E12000 0x10C
DATA0_WR_DATA_SLAVE_RATIO_1 0x44E12000 0x124
0x44E12000
DATA1_RD_DQS_SLAVE_RATIO_1 0x44E12000 0x171
DATA1_WR_DQS_SLAVE_RATIO_1 0x44E12000 0x185
0x44E12000
DATA1_WRLVL_INIT_RATIO_1 0x44E12000 0x199
DATA1_GATELVL_INIT_RATIO_1 0x44E12000 0x1A5
DATA1_FIFO_WE_SLAVE_RATIO_1 0x44E12000 0x1B1
DATA1_WR_DATA_SLAVE_RATIO_1 0x44E12000 0x1C9
DDR_PHY_CTRL_2 0x4C000000 0xEC

with regards

sinthu raja

  • 0
    TI__Guru**** 393215 points
    Registers that are not specified in the TRM should not be used by the customer.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 260 points

    Could I please double-check this, as many of these registers do appear in the TI-supplied AM3358 gel files and other code.  In particular in the gel file I see the DDR_PHY_CTRL_2 register is set to the same value as DDR_PHY_CTRL_1.

    Are you certain it is safe to ignore these unspecified registers and that DDR3 memory will work reliably if the DDR_PHY_CTRL_2 register is not programmed?

     

  • 0
    Mastermind 8040 points

    The GEL file simply contains a generic list of EMIF/PHY registers, regardless of whether they are to be used.

    The DDR_PHY_CTRL registers provide control signals from the EMIF to the PHY.  As far as I know the current DDR2/3 phys make no use of the DDR_PHY_CTRL_2 signals (the old DDR1/2 phy did).  Setting it to the same value as DDR_PHY_CTRL_1 is almost certainly an error.

    The SLAVE_RATIO registers are actually 64-bit, and the _1 suffixed registers you listed are their high words.  The registers contain a 10-bit field per rank (chip select), so you'd need the high words if you have four ranks.  The AM335x supports only a single rank, so those high words are irrelevant.

    All of the SLAVE_RATIO registers (not just those of the command macros) also have associated SLAVE_FORCE (32-bit) and SLAVE_DELAY (64-bit) registers, but they are obscure and I've never seen any documentation on their purpose.  They are probably better left alone.

  • 0 in reply to Matthijs van Duin
    Intellectual 260 points

    Hi Matthijs,

    Many thanks for the clarification.  We'll ensure our code avoids these unspecified registers.

    Regards,

    Chris