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2Gb DDR3L

Avinash Neethi1
Expert 2125 points


Hi All,

           Currently we are working on C6678 processor. We are using DDR3L, Part Number(MT41K128M16JT IT:k). We are providing 1.5v for VDD of DDR3L chip. Whether C6678 support DDR3L chip what we have mentioned above. If it support what are the changes has to be done in the GEL File for DDR3L to access the memory successfully.

           We are facing a issue which we want to rectify as soon as possible. Can any one reply as soon  as possible.

Regards,

Avinash N

  • 0
    TI__Mastermind 42545 points

    Hi Avinash,

    The Jedec specification for DDR3L defines operation at both 1.35V and 1.5V so the part you referenced should be compatible with the C6678 in 1.5V compatible mode. The Micron data sheet confirms that the part is 'backward-compatible to VDD=VDDQ=1.5V'. It also states that you should use the timing numbers found in the 1.5V SDRAM data sheet. Those are the numbers you will need to complete the PHY calc and reg calc spreadsheets for your design.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 2125 points

    Hi Bill,

                Thanks for the immediate response. We had downgraded the speed from 1333MT/s to 800MT/s then we can able to access the memory. I have certain doubts in the GEL file . We have configured the clock of the DDR3L for 800MT/s as,    

     unsigned int PLLM_DDR = 11;
     unsigned int PLLD_DDR = 0;

    and we have calculated the partial automatic leveling  for 800MT/s as ,

        DATA0_WRLVL_INIT_RATIO = 0x57;
        DATA1_WRLVL_INIT_RATIO = 0x57;
        DATA2_WRLVL_INIT_RATIO = 0x5F;
        DATA3_WRLVL_INIT_RATIO = 0x5F;
        DATA4_WRLVL_INIT_RATIO = 0x72;
        DATA5_WRLVL_INIT_RATIO = 0x72;
        DATA6_WRLVL_INIT_RATIO = 0x7C;
        DATA7_WRLVL_INIT_RATIO = 0x7C;
        DATA8_WRLVL_INIT_RATIO = 0x69;

        DATA0_GTLVL_INIT_RATIO = 0x8D;
        DATA1_GTLVL_INIT_RATIO = 0x8D;
        DATA2_GTLVL_INIT_RATIO = 0x95;
        DATA3_GTLVL_INIT_RATIO = 0x95;
        DATA4_GTLVL_INIT_RATIO = 0xA8;
        DATA5_GTLVL_INIT_RATIO = 0xA8;
        DATA6_GTLVL_INIT_RATIO = 0xB2;
        DATA7_GTLVL_INIT_RATIO = 0xB2;
        DATA8_GTLVL_INIT_RATIO = 0x9F;

    and we have calculated the timing values for 1333MT/s as,

        DDR_SDRFC    = 0x00005161;   

        DDR_SDTIM1   = 0x13337834;
        
        DDR_SDTIM2   = 0x30717FE3;
        
        DDR_SDTIM3   = 0x559F86AF;
     
        DDR_DDRPHYC  = 0x0010010B;

        DDR_ZQCFG    = 0x70074c1f;

        DDR_PMCTL    = 0x0;

        DDR_SDRFC = 0x000030D3;

        DDR_SDCFG    = 0x63055AB2;
        
        Delay_milli_seconds(1);

        DDR_SDRFC = 0x00000A2C;
     

    . The above parameters are used in the GEL file what we have tested.

    Question:

    1. While using DDR3 Chip, we can able to access the DDR3 in 1333MT/s and When we changed to DDR3L We can't able to achieve the full speed. what can be the reason?

    2. Are there any changes has to be done to achieve full speed of 1333MT/s?

    3. Any of the Customers or TI has tried DDR3L with C6678 combination and achieved Full-speed access of DDR3L 1333MT/s?

    Regards,

    Avinash N

  • 0 in reply to Avinash Neethi1
    Intellectual 280 points

    Avinash,  I saw you posted a question related to the DDR3L  problems  I was having on my post.. See link below

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/287616/1057220.aspx#1057220

    Please read and provide some feedback from your end. 

    Thank you

    Larry