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Question about DDR3 initialization during SPI boot

g.f.
Guru 15520 points

Hi,

I have a question about C6670 SPI boot.

In our custom board, it boots up from SPI NOR Flash.
If all code and data is loaded to L2SRAM, it boots with no problem.
But if all code/data is loaded to DDR3, boot will be done but  the code/data in DDR3 is incorrect.

I made a DDR configuration table as following E2E:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/288354/1012614.aspx#1012614

After boot, I checked the DDR3 Memory Controller Registers from CCS Memory Browser
and it was set correctly. But it
I guess that DDR configuration table's parameter is not enough for initializing DDR3.
Isn't DDR3 Configuration Register 0 to 24 need to be initialized during RBL?
If it is true, how to configure it? It seem there is no examples and documentation.

Please give me an advice and information.

best regards,
g.f.

  • 0
    TI__Guru** 116170 points

    Yes, DDR3 leveling is not done using the C6670 ROM code so it may be useful for you to re-initialize DDR after your primary boot image is loaded in in memory and then increase the DDR3 speed . Could you please specify the values you are using in the DDR3 configuration table. Can you please initialize the DDR PLL to lower frequencies and try this experiment again.

    Do the values in the DDR3 configuration register space match with the values you have in the GEL file you use to connect to the custom board. If the DDR3 part on your custom board is different from the EVM, have you checked that you have made the necessary changes to settings of the DDR3configuration registers

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 15520 points

    Hi Rahul,

    Thank you for the reply and sorry for the delay.

    The following value is what we used for the DDR3 configuration Table:
    ////////////////////////////////////////////
    pllPrediv  = 0
    pllMult    = 20
    pllPostDiv = 2

    SDRAM CFG    = 0x6126AAB0
    SDRAM CFG2        = 0x0
    SDRAM Refresh Ctl = 0x00001458
    SDRAM TIM1        = 0x1335887D
    SDRAM TIM2        = 0x40717FEB
    SDRAM TIM3        = 0x559F86AF
    lpDdrNvmTiming    = 0x0
    powerManageCtl    = 0x0
    iODFTTestLogic    = 0x0
    performCountCfg   = 0x0
    performCountMstRegSel = 0x0
    readIdleCtl       = 0x0
    sysVbusmIntEnSet  = 0x0
    SDRAM ZQCFG       = 0x70073214
    tempAlterCfg      = 0x0
    DDRPHYCTRL1       = 0x0010010F
    ddrPhyCtl2        = 0x0
    priClassSvceMap   = 0x0
    mstId2ClsSvce1Map = 0x0
    eccCtl            = 0x0
    eccRange1         = 0x0
    eccRange2         = 0x0
    rdWrtExcThresh    = 0x0
    ////////////////////////////////////////////////

    >>Yes, DDR3 leveling is not done using the C6670 ROM code so it may be useful
    >>for you to re-initialize DDR after your primary boot image is loaded in memory
    >>and then increase the DDR3 speed .

    In which memory should primary boot image be loaded?
    Do we need to allocate the Core0's code/data in to L2RAM
    so that it won't access DDR3 during Primary boot?

    >>Do the values in the DDR3 configuration register space match with
    >>the values you have in the GEL file you use to connect to the custom board.

    Yes, it matched.

    >>If the DDR3 part on your custom board is different from the EVM,
    >>have you checked that you have made the necessary changes to settings of
    >>the DDR3configuration registers

    Yes, we changed the setting of the DDR3 register for the customer board.
    If we connect the board to CCS and load the customer GEL file, we could access DDR3 with no problem.

    best regards,
    g.f.