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Pcie_BARMASK

NITHIN BOJJA
Intellectual 505 points

Hi,

I have a doubt on Pcie BAR Mask. In the PCIe use cases application note(SPRABK8) it is given that to write to BAR mask register "enable DBI_CS2, write BAR0 MASK register = 0x0000_3FFF, disable
DBI_CS2, write BAR0 = 0xFFFF_FFF0; BAR0 should be read as 0xFFFF_C000( page number 11 )". I am not getting how 0xFFFF_FFF0 is becoming FFFF_C000. Can any one explain how masking is happening with the example.

Thanks in advance,

Nithin

  • 0
    TI__Guru* 95265 points

    I thought this is explained in the document: "One way to verify if the BAR Mask registers have been set correctly is to write the pattern values into BAR registers and see if the bits have been masked correctly. For example, enable DBI_CS2, write BAR0 MASK register = 0x0000_3FFF, disable DBI_CS2, write BAR0 = 0xFFFF_FFF0; BAR0 should be read as 0xFFFF_C000 because the lower bits of BAR0 have been masked."

    From math: 0xFFFF_FFF0 & (~ 0x0000_3FFF) = 0xFFFF_FFF0 & 0xFFFF_C000 = 0xFFFF_C000.

    Regards, Eric

     

  • 0 in reply to lding
    Intellectual 505 points

    Thank You Eric