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Pcie_Read

NITHIN BOJJA
Intellectual 505 points


Hi,

I am trying to implement PCIe interface between TMS320TCI6670 and ALTERA Cyclone 4 FPGA. I have understood that the root complex maps the data from the source buffer to the Pcie base address(0x60000000) and outbound address translation from pcie base address 0x60000000 to 0x70000000, as outbound address is 0x70000000. Now my FPGA is Endpoint and the FPGA IP BAR 1  has 0x00200000 . If i put this address as my DSP outbound address(replacing 0x70000000 to 0x00200000), is it enough?.How to configure BAR MASK register?, as example PCIe code has 0x0FFFFFFF as BAR MASK register for 0x70000000 out bound value.What will be our BAR MASK Register value? Can any one explain this. Your kind help is appreciated.

Thank You,

Regards,

Nithin B

  • 0
    TI__Guru* 95265 points

    I am not familiar with PCIE setup of the Altera FPGA, but assuming it follows the same rule as for DSP. If you replaced the 0x7000_0000 to 0x0020_0000 on DSP side, then the PCIE address generated would be somthing like:

    0x6000_0000 DSP side = 0x0020_0000 to EP side via PCIE bus.

    0x6000_0004 DSP side = 0x0020_0004 to EP side

    0x6000_0008 DSP side = 0x0020_0008 to EP side

    ....

    In DSP side (RC), the PCIE outbound region is 256 MB (starting from 0x6000_0000 to 0x6FFF_FFFF), that is why we used a BAR MASK of 0x0FFF_FFFF.

    For your EP, you need to know how big memory region you want to map into DSP, then setup the BAR mask for BAR1. For example, if you only want 512KB, then the BAR1 mask would be 0x0007_FFFF. Then, PCIE address 0x0020_0000 --- 0x0027_FFFF will be accept by FPGA, above 0x0027_FFFF will be rejected.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 505 points

    Hi Eric,

    Thank you for the reply. I am trying pcie example project with two evms connected with the breakout board. As my FPGA address is 0x00200000 i am taking this as my outbound address(BAR1) and putting BAR Mask as 0x0007FFFF. When i am trying this data transfer is not happening. If i put my address(BAR1) as 0x02000000 it is working fine(data transfer happening between two evms) with the same BARMask(512KB). Why it is not working with the BAR1 address 0x00200000.

    Thank you very much for your kind help,

    with Regards,

    Nithin

  • 0 in reply to NITHIN BOJJA
    Intellectual 505 points

    Hi Eric,

     I was able to make the data transfer between two EVMs using outbound address as 0x00200000 (BAR1) and putting BAR Mask as 0x000FFFFF (1 MB). The issue was initially I have put OBSIZE as 8 MB but when I changed to 1 MB, it was working fine.  Now I want to do data transfer on my custom board where i am implementing PCIE interface between TMS320TCI6678 (Root complex) and Altera CYCLONE 1V FPGA.(End point). FPGA's BAR address range is 0X00200000-0X00200FFF (4 KB). What should be my OBSIZE and BAR Mask value in this case? (Actually OBSIZE has values 1MB/2 MB/4 MB/8MB but I have BAR address range of 4 KB).

    Thanks in advance,

    Nithin

  • 0 in reply to NITHIN BOJJA
    TI__Guru* 95265 points

    Nithin,

    I don't know why OB size changed from 8 MB to 1 MB made the PCIE working between 2 EVMs. The smallest OB size is 1 MB in configuration of OB_SIZE (0x2180_0030).

    In your RC side (TI DSP): can you configure OB size as 1 MB and the first OB translation region to (0x0020_0000) and enable this region (so address 0x2180_0200 = 0x0020_0001).

    In your EP side (FPGA): configure BAR 1 to 0x0020_0000 with BAR_MASK 4KB (0x0000_0FFF). If you have some inbound translation also configure those.

    Then when PCIE link is up, will a poke to DSP's 0x6000_0000 memory showing up in FPGA's memory?

    Regards, Eric